Abstract
In this work, for the first time, the DC characteristics and Analog/RF performance of negative capacitance (NC) Silicon-on-insulator (SOI) junctionless transistor (JLT) have been investigated including quantum confinement effects. In NC transistors, ferroelectric materials are used in the gate-stack to improve the switching characteristics. The Metal-Ferroelectric-Metal-Insulator-semiconductor (MFMIS) gate-stack structure has been simulated with the help of 1D Landau Khalatnikov (LK) equation to incorporate the effect of negative capacitance with SOI JLT. The impact of varying the temperatures in the range 300–380 K and ferroelectric layer thickness (tf) of 0 to 4.5 nm on the device characteristics are studied. The analog and RF characteristics such as transconductance (gm) and cut-off frequency (ft) of NC SOI JLT show better performance over SOI JLT. A minimum subthreshold swing (SS) of 12.77 mV/decade and ft of 590 GHz has been observed at 300 K for a channel length (L) of 14 nm with tfof 4.5 nm. The characteristics of NC SOI JLT are evaluated by coupling the 1D LK equation with the simulated results of SOI JLT which are obtained using 2D device simulator AtlasTM from Silvaco.
Published Version
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