Negative Capacitance FinFETs Research Articles

Interface traps in the sub-3 nm technology node: A comprehensive analysis and benchmarking of negative capacitance FinFET and nanosheet FETs - A reliability perspective from device to circuit level

Interface traps play a significant role in shaping the performance and reliability of semiconductor devices, particularly in advanced technologies such as Negative Capacitance based FinFET and Nanosheet (NS) FET. Hence, for the first time, using well calibrated TCAD models, we benchmark and explore into the analysis of interface traps in NC-FinFET and NC-NSFET devices at the sub-3 nm technology node, focusing on their effects on digital, analog/RF performance parameters. The investigation is mainly focussed on: (a) Positioning of acceptor (EV + 1 - EV-0.4) and donor (EC + 0.2 - EC-1.5) trap locations in the energy band (b) variation in acceptor and donor interface trap concentration (c) design of Common Source (CS) amplifier for analog integrated circuits. In addition, we explored a design space to achieve optimal capacitance matching, targeting the NC effect for an optimized device design. Our findings showed a significant improvement in ION/IOFF ratio by ~9× for NC-NSFET when compared to NC-FinFET with change in acceptor trap locations. The NC-FinFETs demonstrated a resilient intrinsic gain (AV) profile, making them suitable for high-speed amplifiers. Varying donor trap locations had minimal impact on NC-NSFET but slightly affected NC-FinFET's intrinsic gain profile. Moreover, increasing acceptor trap concentration improved digital performance, with NC-NSFET outperforming NC-FinFET and the analog/RF performance favored lower trap concentrations. In addition, NC-FinFETs were more resilient to increased donor traps concentration than NC-NSFETs. Further, the CS amplifier-based NC acceptor devices offered effective amplification and power-saving features, making them ideal for IoT and biomedical applications reliant on battery voltages.

Effects of the VGS sweep range on the short channel effect in negative capacitance FinFETs

Effects of the VGS sweep range on the short channel effect in negative capacitance FinFETs

Unveiling the reliability of negative capacitance FinFET with confrontation of different HfO2-ferroelectric dopants

The CMOS compatibility of Negative Capacitance (NC) FETs has been enhanced tremendously after introducing a thin film-doped HfO2 as a ferroelectric (FE) layer. For a given FE layer, the NC property is governed by specific HfO2 dopants (e.g., La, Zr, Al, Sr, Gd, Y, and Si). Thus, the TCAD simulation considerably depends on the dopant-specific Landau parameters (αx,βx,γx,ρx,gx), and its solidity needs proper attention. Further, the reliability of the NC devices is severely affected by process variations, i.e., interface trap charges, work function variation, random dopant fluctuation, and ambient temperature (external), which modulates the device threshold voltage (Vth); in turn, the device aging. In this paper, using well-calibrated TCAD models, we investigated reliability for the different dopant-specific NC-FinFET, in terms of Vth, ON current (ION), and OFF current (IOFF) modulation induced by: (i) the interface trap variability (ITV) considering the different trap concentration and energy location; (ii) the work function variability (WFV) considering different metal grain sizes (Gr); (iii) the random dopant fluctuations (RDF); and (iv) the ambient temperature. In this way, the device aging is calculated by inspecting Vth shift by ±50mV. These investigations pave the path for realizing a reliable NC-FinFET design.

Impact of Buried Gate Oxide on the Electrical Performance of Negative Capacitance FinFETs: Design Perspectives

Impact of Buried Gate Oxide on the Electrical Performance of Negative Capacitance FinFETs: Design Perspectives

A proof of concept for reliability aware analysis of junctionless negative capacitance FinFET-based hydrogen sensor

This work demonstrates the reliability-aware analysis of the Junctionless negative capacitance (NC) FinFET employed as a hydrogen (H2) gas sensor. Gate stacking of the ferroelectric (FE) layer induces internal voltage amplification owing to the NC property, thus, improving the sensitivity of the baseline junctionless FinFET. A well-calibrated TCAD model is used to investigate the sensing characteristics of the proposed FinFET-based H2 sensor by employing the palladium (Pd) metallic gate as a sensing element. The mechanism involves the transduction of H2 gas molecules over the metal gate; due to the diffusion process, some atomic hydrogen diffuses into the metal. The H2 gas absorption at the metal surface causes a dipole layer formation at the gate and oxide interface, which changes the metal gate work function. As a result, this change in the work function can be used as a sensing parameter of the proposed gas sensor. Further, the threshold voltage and other electrical characteristics, such as output conductance, transconductance, and drain current are examined for sensitivity analysis for both NC and without NC JL FinFET at different pressure ranges, keeping the temperature constant (i.e. 300 K). The device variation, i.e. Fin thickness, Fin height, doping and thickness of HfO2 ferroelectric layer, etc, on sensor sensitivity has been evaluated through extensive simulation. This paper also presents a detailed investigation of the sensor’s reliability in terms of work function variation, random dopant fluctuation, trap charges, and device aging, i.e. end of a lifetime. At last, the acquired results are compared with earlier reported data, which justifies the profound significance of the proposed junctionless negative capacitance FinFET-based H2 gas sensor.

Performance estimation of non-hysteretic negative capacitance FinFET based SRAM

In this paper, a detailed evaluation of negative capacitance FinFET (NC-FinFET) based volatile static random access memory (6T-NCSRAM) is carried out by utilizing L-K equation for ferroelectric and calibrated BSIM-CMG model with 14 nm conventional FinFET to form NC-FinFET. Static and dynamic behavior of NC-FinFETs is explored and evaluated at different ferroelectric thickness. At supply voltage scaling, important SRAM performance metrics such as stability at different operation condition (hold, read and write mode) and standby leakage power were evaluated. When compared to traditional FinFET based SRAM, 6T-NCSRAM exhibits distinct behavior during low and high supply voltages. Moreover, the effect of wordline (WL) voltage pulse variation on 6T-NCSRAM is captured and minimum RC multiplier of 2RC is found to avoid functional failure of 6T-NCSRAM.

Analog/RF and Linearity Performance Assessment of a Negative Capacitance FinFET Using High Threshold Voltage Techniques

Analog/RF and Linearity Performance Assessment of a Negative Capacitance FinFET Using High Threshold Voltage Techniques

Reliability of TCAD study for HfO2-doped Negative capacitance FinFET with different Material-Specific dopants

Attaining the ferroelectric (FE) polarization in a thin HfO2 layer using a specific dopant is a widely adopted way to realize Negative Capacitance (NC) FET. In a general TCAD simulation study of NC-based devices, the NC property of the FE layer is strongly dependent on the values of Landau parameters (α,β,γ,ρ,g), which are unique for specific dopants and FE thickness. In this paper, for the first time, we investigated the reliability of TCAD simulations with which NC FinFET is simulated for a specific dopants-based FE-HfO2 layer. The possible dopants used to realize a thin-HfO2 layer as a FE layer are Al, Gd, La, Si, Sr, Y, and Zr. Each dopant has different (α,β,γ,ρ,g) and thus offers a different NC regime of operation, i.e., S-curve. α and β are the dominant parameters if we consider the uniform polarization under quasi-static analysis. Further, the change in ambient temperature alters the value of α, resulting in changes in the NC-state. Hence, for the reliable TCAD-based NC study, the precise selection of Landau parameters and dopants is needed for optimized performances.

Mathematical Modeling and Performance Evaluation of 3D Ferroelectric Negative Capacitance FinFET

Ferroelectric negative capacitance materials have now been proposed for lowering electronics energy dissipation beyond basic limitations. In this paper, we presented the analysis on the performance of negative capacitance (NC) FinFET in comparison with conventional gate dielectrics by using a separation of variables approach, which is an optimal quasi-3D mathematical model. The result has been signified steeper surface potential (ψ), lower threshold voltage (Vth), 1.2 mA of on-state current (Ion), and enhanced immunity of negative capacitance FinFET against short channel effects (SCE’s) like 35.3 mV/V of drain-induced barrier lowering (DIBL), 60 mV/dec of subthreshold swing (SS) along with smallest off state current (Ioff) among another conventional gate dielectric. Hence, NC FinFET can be a potential candidate for low power and high-performance device.

Role of temperature on linearity and analog/RF performance merits of a negative capacitance FinFET

Temperature plays a decisive role in semiconductor device performance and reliability analysis. The effect is more severe in a negative capacitance (NC) transistor, as the temperature modulates the ferroelectric polarization, implicitly included by the Landau coefficients (α, β, γ) in Technology Computer Aided Design (TCAD) simulations. In this paper, through TCAD simulations, the role of varying ambient temperature is investigated in the linearity and analog/radio-frequency (RF) merits of NC-FinFET. The varying temperature modulates the carrier mobility, the semiconductor bandgap, and the Landau parameter (α). We analyzed the analog/RF and linearity metrics, such as total gate capacitance (C gg), transconductance (g m), unity gain cut-off frequency (f T), the transconductance-frequency product, gain-bandwidth product, higher-order transconductance (g m2 and g m3), voltage intercept points, third-order power intercept and intermodulation points, and 1 dB CP using well-calibrated TCAD models. Our analysis reveals that these parameters are strongly dependent on temperature and the NC span (defined by using S-curve) shrinks with the rise in temperature. Finally, a source follower and three-stage ring oscillator are designed to test the frequency compatibility of the AC simulation for varying temperatures.

Exploration and Device Optimization of Dielectric–Ferroelectric Sidewall Spacer in Negative Capacitance FinFET

Gate sidewall spacers, a pathway to the fringing fields, play a crucial role in the device design. In this article, using well-calibrated TCAD models, we have explored the impact of a sidewall ferroelectric (FE) spacer on a negative capacitance (NC) FinFET. In the proposed study, the FE layer is present beneath the gate electrode and at the spacer region that operates in the NC region. Through three novel FE–dielectric (FE–DE) spacer configurations, we found that proficient electrostatic control can be attained with the optimized stacked placement of the spacers. The fringing fields alter the FE polarization present at the spacer stack and modulates the channel charge, which is a prime objective of this work. Furthermore, we have varied the FE parameters, drain doping, and extension length to optimize the proposed FE–DE spacer configurations. We have done mixed-mode simulations to design an inverter and a three-stage ring oscillator to emphasize our results. The optimized spacer configuration shows~3.9% overshoot due to higher gate capacitance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{GG}$ </tex-math></inline-formula> ); however, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm{ON}} / I_{\mathrm{OFF}}$ </tex-math></inline-formula> ratio is approximately twic than that of the baseline counterpart. The results reveal that the optimized spacer configuration also mitigates the negative differential resistance (NDR), which allows the NC-based devices to be an efficient candidate for analog applications.

Demonstration of Improved Short Channel Performance Metrics for Ferroelectric Concentric Negative Capacitance FinFET

Demonstration of Improved Short Channel Performance Metrics for Ferroelectric Concentric Negative Capacitance FinFET

Quasi-analytical model of surface potential and drain current for trigate negative capacitance FinFET: a superposition approach

Negative capacitance (NC) obtained from the ferroelectric polarization switching is a widely adopted approach for the realization of low power, high-performance devices. In this paper, for the first time, we have developed a 3D quasi-analytical model for the surface potential and drain current of the trigate NC-FinFET using the superposition approach. Till date, only double gate (DG) uniformly doped NC-FinFET structures have been explored, which does not reveal the practicality of the device. Therefore, we perform an extensive device evaluation: (a) by solving the Poisson’s equation separately for the side gates (DG) and the top gate to acquire a complete model for trigate FinFET using the superposition principle; (b) to mimic the actual source/drain (S/D) doping, we included Gaussian doping in our proposed model; (c) with the incorporation of the laterally extended gate and S/D underlap. The model data are found in good agreement with the well-calibrated simulation data. We have taken the parabolic approximation method and appropriate boundary conditions to solve the Poisson’s equation.

On the performance of hafnium-oxide-based negative capacitance FinFETs, with and without a spacer

This paper reports a thorough investigation of the impacts of a spacer dielectric on the performance of HfO2-ferroelectric-based negative capacitance (NC)-FinFETs for 10 nm technology (gate length 22 nm) as per International Roadmap for Devices and Systems with in comparison with similarly-sized conventional FinFETs by means of an industry standard technology computer aided design tool. It is found that, although a high-k spacer results in improved subthreshold swing (SS) and I ON, it increases delay due to enhanced gate capacitance for both types of devices. In spite of having higher gate capacitance for a given spacer, the delay is lower for the NC devices than the conventional devices with identical I OFF, which is due to higher I ON in such devices. Comparing with the baseline FinFET; I ON, SS, threshold voltage, delay and power dissipation of NC-FinFET have been found to improve by 69%, 7%, 5%, 14% and 9% respectively, when Si3N4 spacer is used. Implications of spacer on V DD scalability, delay and power dissipation of NC-FinFETs have also been investigated in one-to-one comparison with similarly-sized conventional FinFETs. If identical delay is considered in both the devices, higher active power dissipation due to enhanced gate capacitance is a concern for HfO2-ferroelectric-based NC-FinFETs.

Mitigating DIBL and Short-Channel Effects for III-V FinFETs With Negative-Capacitance Effects

This paper, based on the IRDS 2022 technology node, investigates the DIBL and short-channel effects for InGaAs negative-capacitance FinFETs (NC-FinFETs) through a theoretical subthreshold drain current model considering key effects including negative capacitance, quantum confinement and source-to-drain tunneling. Due to the impact of negative capacitance on the source-to-drain potential profile, tunneling distance and its drain-bias dependence, the short-channel effects can be substantially improved for InGaAs NC-FinFETs. Our study indicates that, with the larger NC effect of the III-V channel, the gap in DIBL and subthreshold swing between InGaAs and Si FinFETs in the sub-20 nm gate-length regime can become much closer. Our study may provide insights for future supply-voltage/power scaling of logic devices with high-mobility channel.

Insights into the operation of negative capacitance FinFET for low power logic applications

In the incessant search to overcome the power densities and energy efficient limitations, performance matrix of emerging electronic devices are being explored inevitably to find the alternatives of MOSFETs. We investigated and compared the delay and energy performance matrices of fin-shaped FET and negative capacitance FinFET (NC-FinFET) based devices and circuits designed on the same technology node. The improvement in the performance of NC-FinFET based CMOS circuits is enhanced due to the negative capacitance’s negative DIBL by employing a industry standard BSIM-CMG model. After analyzing at the device-level, detailed evaluation is carried out at logic level for embedded inverter chain, three-stage ring oscillators (ROs), and 2-bit ripple carry adders (RCA) for frequencies ranging between 10 kHz–1 GHz. Our findings revealed that the NC-FinFET based circuit has a lower delay for a given range of operating frequencies and saves a significant amount of power when compared to baseline FinFET, making NC-FinFET desirable for low power digital logic applications.

A Novel Negative Capacitance FinFET With Ferroelectric Spacer: Proposal and Investigation.

In this letter, for the first time, we investigate the role of Ferroelectric (FE) spacer in a negative capacitance (NC) FinFET. Using well-calibrated TCAD models, we found that instead of placing a dielectric (DE) spacer, if we use an FE spacer, enhanced electric field due to FE polarization can be achieved, thereby producing a higher ON-current. The fringing fields polarize the FE spacer and result in voltage amplification, which lowers the effective barrier and increases the current driving capability. ON-current of the proposed configuration, i.e., FE spacer at the source (S) side and DE spacer at the drain (D) side, is ~30% higher than the baseline FinFET. In this work, we have also proposed four different spacer placement configurations to realize better performances in terms of higher ON-current, mitigation of negative differential resistance (NDR) and better subthreshold slope (SS), and so on. We found that the optimized performance can be attained by placing an FE and DE spacer at the S and D end, respectively. We also evaluated a design space window for a good capacitance match to achieve NC effect for optimized device design.

Investigation of time domain characteristics of negative capacitance FinFET by pulse-train approaches

The HfO2-based ferroelectric field effect transistors (FeFET) have been widely studied for their ability in breaking the Boltzmann limit and the potential to be applied to low-power circuits. This article systematically investigates the transient response of negative capacitance (NC) fin field-effect transistors (FinFETs) through two kinds of self-built test schemes. By comparing the results with those of conventional FinFETs, we experimentally demonstrate that the on-current of the NC FinFET is not degraded in the MHz frequency domain. Further test results in the higher frequency domain show that the on-state current of the prepared NC FinFET increases with the decreasing gate pulse width at pulse widths below 100 ns and is consistently greater (about 80% with NC NMOS) than the on-state current of the conventional transistor, indicating the great potential of the NC FET for future high-frequency applications.

Recent Advances in Negative Capacitance FinFETs for Low-Power Applications: A Review.

In the contemporary era of Internet-of-Things (IoT), there is an extensive search for competent devices which can operate at ultralow voltage supply. Due to the restriction of power dissipation, a reduced sub-threshold swing-based device appears to be the perfect solution for efficient computation. To counteract this issue, negative capacitance fin field-effect transistors (NC-FinFETs) came up as the next-generation platform to withstand the aggressive scaling of transistors. The ease of fabrication, process-integration, higher current driving capability, and ability to tailor the short-channel effects (SCEs) are some of the potential advantages offered by NC-FinFETs that attracted the attention of researchers worldwide. The following review emphasizes how this new state-of-art technology supports the persistence of Moore's law and addresses the ultimate limitation of Boltzmann tyranny by offering a sub-threshold slope (SS) below 60 mV/decade. The article primarily focuses on two parts: 1) the theoretical background of negative capacitance (NC) effect and FinFET devices and 2) the recent progress done in the field of NC-FinFETs. It also highlights the crucial areas that need to be upgraded, to mitigate the challenges faced by this technology and the future prospects of such devices.

S-Curve Engineering for ON-State Performance Using Anti-Ferroelectric/Ferroelectric Stack Negative-Capacitance FinFET

This work investigates the S-curve engineering by exploiting the anti-ferroelectric (AFE)/ferroelectric (FE) stack negative-capacitance FinFET (NC-FinFET) to improve both the subthreshold swing and ON-state current ( I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ). The capacitance matching and ON-state performance are evaluated using a short-channel AFE/FE stack NC-FinFET model. Our study indicates that the AFE/FE gate-stack can theoretically achieve surprising improvements to the OFF-state current ( I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> relative to International Roadmap for Devices and Systems (IRDS) projections. There is a significant long-term advantage to integrated circuit (IC) power consumption and speed if materials with certain AFE and FE characteristics can be developed and introduced into IC manufacturing.