Interface traps in the sub-3 nm technology node: A comprehensive analysis and benchmarking of negative capacitance FinFET and nanosheet FETs - A reliability perspective from device to circuit level

Abstract

Interface traps play a significant role in shaping the performance and reliability of semiconductor devices, particularly in advanced technologies such as Negative Capacitance based FinFET and Nanosheet (NS) FET. Hence, for the first time, using well calibrated TCAD models, we benchmark and explore into the analysis of interface traps in NC-FinFET and NC-NSFET devices at the sub-3 nm technology node, focusing on their effects on digital, analog/RF performance parameters. The investigation is mainly focussed on: (a) Positioning of acceptor (EV + 1 - EV-0.4) and donor (EC + 0.2 - EC-1.5) trap locations in the energy band (b) variation in acceptor and donor interface trap concentration (c) design of Common Source (CS) amplifier for analog integrated circuits. In addition, we explored a design space to achieve optimal capacitance matching, targeting the NC effect for an optimized device design. Our findings showed a significant improvement in ION/IOFF ratio by ~9× for NC-NSFET when compared to NC-FinFET with change in acceptor trap locations. The NC-FinFETs demonstrated a resilient intrinsic gain (AV) profile, making them suitable for high-speed amplifiers. Varying donor trap locations had minimal impact on NC-NSFET but slightly affected NC-FinFET's intrinsic gain profile. Moreover, increasing acceptor trap concentration improved digital performance, with NC-NSFET outperforming NC-FinFET and the analog/RF performance favored lower trap concentrations. In addition, NC-FinFETs were more resilient to increased donor traps concentration than NC-NSFETs. Further, the CS amplifier-based NC acceptor devices offered effective amplification and power-saving features, making them ideal for IoT and biomedical applications reliant on battery voltages.