Negative Bias Temperature Instability Lifetime Research Articles

Investigation of degradation and recovery characteristics of NBTI in 28-nm high-k metal gate process

Degradation induced by the negative bias temperature instability (NBTI) can be attributed to three mutually uncoupled physical mechanisms, i.e., the generation of interface traps (ΔV IT), hole trapping in pre-existing gate oxide defects (ΔV HT), and the generation of gate oxide defects (ΔV OT). In this work, the characteristic of NBTI for p-type MOSFET fabricated by using a 28-nm high-k metal gate (HKMG) process is thoroughly studied. The experimental results show that the degradation is enhanced at a larger stress bias and higher temperature. The effects of the three underlying subcomponents are evaluated by using the comprehensive models. It is found that the generation of interface traps dominates the NBTI degradation during long-time NBTI stress. Moreover, the NBTI parameters of the power-law time exponent and temperature activation energy as well as the gate oxide field acceleration are extracted. The dependence of operating lifetime on stress bias and temperature is also discussed. It is observed that NBTI lifetime significantly decreases as the stress increases. Furthermore, the decrease of charges related to interface traps and hole detrapping in pre-existing gate oxide defects are used to explain the recovery mechanism after stress.

Investigation of Negative Bias Temperature Instability Effect in Nano PDSOI PMOSFET.

The Negative Bias Temperature Instability (NBTI) effect of partially depleted silicon-on-insulator (PDSOI) PMOSFET based on 130 nm is investigated. First, the effect of NBTI on the IV characteristics and parameter degradation of T-Gate PDSOI PMOSFET was investigated by accelerated stress tests. The results show that NBTI leads to a threshold voltage negative shift, saturate drain current reduction and transconductance degradation of the PMOSFET. Next, the relationship between the threshold voltage shift and stress time, gate bias and temperature, and the channel length is investigated, and the NBTI lifetime prediction model is established. The results show that the NBTI lifetime of a 130 nm T-Gate PDSOI PMOSFET is approximately 18.7 years under the stress of VG = −1.2 V and T = 125 °C. Finally, the effect of the floating-body effect on NBTI of PDSOI PMOSFET is investigated. It is found that the NBTI degradation of T-Gate SOI devices is greater than that of the floating-body SOI devices, which indicates that the floating-body effect suppresses the NBTI degradation of SOI devices.

Influence of Buried Oxide Si+ Implantation on TID and NBTI Effects for PDSOI MOSFETs

The total ionization dose (TID) effect and negative bias temperature instability (NBTI) effect of 130-nm partially-depleted silicon-on-insulator (PDSOI) MOSFETs fabricated on hardened wafers with silicon ion implantation and unhardened wafers are investigated. A TID-hardened PDSOI MOSFET up to 1 Mrad(Si) is obtained by Si+ implantation in buried oxide (BOX). The hardening benefits from the electron traps in the BOX introduced by Si+ implantation. Although the radiation hardening process has a rare impact on nominal electrical characteristics of the device before irradiation, it will affect the NBTI reliability, which is manifested as the decrease in the NBTI lifetime for the radiation-hardened devices. The energy distribution of positive charges built up during NBTI stress is obtained. It proves that more damage-related traps exist near the gate oxide/silicon interface for the radiation-hardened device, which accelerates the threshold voltage shift during the NBTI stress. This conclusion is also verified by the low-frequency noise characteristics.

Research on Negative Bias Temperature Instability Effects Under the Coupling of Total Ionizing Dose Irradiation for PDSOI MOSFETs

The degradation mechanisms for pMOSFETs from a 130 nm partially-depleted silicon on insulator (PDSOI) technology under the combined effects of total ionizing dose (TID) and negative bias temperature instability (NBTI) are investigated. The TID and NBTI related degradations show an opposite trend as gate oxide scaling, which implies the different traps are activated during irradiation and NBTI stress. The radiation-induced traps can affect the NBTI effect of pMOSFET, especially for the ON bias irradiation. The irradiated I/O pMOSFET shows a smaller threshold voltage shift than the un-irradiated device under the same NBTI stress at the early stress stage. It may be contributed to the enhanced Fowler-Nordheim electron injection during NBTI stressing after ON bias irradiation. But the irradiation also increases the time exponent $n$ from 0.11 to 0.13 for Core pMOSFETs and from 0.18 to 0.20 for I/O devices. It means that the NBTI degradations become worse after ON bias irradiation in a long time scale. This phenomenon is attributed to the change of trap characteristics caused by irradiation. As a result, the NBTI lifetime of Core device is reduced by nearly three orders of magnitude and the lifetime of I/O device is reduced by five times after ON bias irradiation at the rated operating voltage.

Dependency of electrical performances and reliability of 28 nm logic transistor on gate oxide interface treatment methods

The effects of precleaning processes by O3 and SC-1 in depositing high-κ gate dielectric are closely investigated in experimental comparison study. The study is made in the p-type MOSFET on the 28 nm technology node in product. O3 cleaning demonstrated significant effects of increasing the effective oxide thickness in the inversion operation mode, reducing the gate leakage, and suppressing the standby leakage current. The electrical performances of PMOSFETs fabricated employing these two different precleaning methods were analyzed, and furthermore, device reliability was evaluated. The negative bias temperature instability lifetime showed 4-fold difference depending on cleaning method.

Overview of Bias Temperature Instability in Scaled DRAM Logic for Memory Transistors

Continued scaling of DRAM technologies has required a limitation of the power dissipation from the logic components on-chip, while downscaling both transistor oxide thickness and gate length. One route to enable further scaling, while circumventing excessive leakage currents, is the integration of high-permittivity ( ${\kappa }$ ) metal-gate (HKMG) components into the logic and high-voltage (e.g., I/O) devices. The requirement of a gate-first flow for devices in the peripheral region introduces significant reliability challenges. Even though Negative Bias Temperature Instability (NBTI) performance of CMOS and memory thermal budget compatible transistors are aligned with conventional HKMG integration with thin oxide devices, it is not the case for thick oxide devices. In particular, it will be shown that strong NBTI lifetime degradation is observed as soon as high- ${\kappa }$ layers are deposited on top of the thick interfacial layer. In this work, a review of the impact of these high- ${\kappa }$ layers on the NBTI high voltage logic for memory devices is presented. The stress induced degradation is correlated to a diffusion of metal atoms from the HKMG gate stack towards the silicon surface. Directions for reliability improvements are then defined. The presence of Nitrogen throughout the HKMG stack can originate either from high- ${\kappa }$ processing or metal-nitride gate electrode. It is shown that preventing nitrogen diffusion towards the Si/SiO2 interface region, together with AlOx and/or F incorporation at the HKMG interface, can tune device threshold voltage and modulate access to donor trap-defect bands. The result of these effects is a vast improvement in NBTI performance. A detailed study of NBTI-degradation, supported by physical analysis, assessing the impact of various tuning components within the stack (interface layer, high- $\kappa $ fluorination and/or cap, metal gate) will be presented. Potential solutions for this reliability challenge will be reported.

Improved electrical characteristics and reliability of p-MOSFET with fluorine implant

The method of fluorine implant directly after a poly gate deposition process step is proposed to improve both electrical characteristics and reliabilities by creating Si-F bonding at a gate oxide interface and negative fixed charged in a gate oxide. Capacitance-voltage (C-V) curve and gate oxide leakage current was used to investigate oxide thickness and flat band voltage (Vfb) shift. Experimental results show fluorine implant induced regrowth of gate oxide ~1 Å and Vfb shift ~−40 mV. Owing to the Vfb shift, ~24 mV of drain induced barrier lowering is improved. Furthermore, gate oxide interface quality was evaluated using charge pumping current and negative bias temperature instability (NBTI), and gate oxide quality was evaluated using time-dependent dielectric breakdown (TDDB). The results show that the fluorine implant process which is prosed in this paper reduced 27% of the interface trap and improved ~0.8 order higher NBTI lifetime. TDDB lifetime showed a slight improvement when using the proposed method. Thus, a controlled fluorine implant step improves both DC electrical characteristics and gate oxide reliabilities. These suggest that the fluorine implant step should be carefully selected when fabricating PMOSFETs.

An Investigation of Field Reduction Effect on NBTI Parameter Characterization and Lifetime Prediction Using a Constant Field Stress Method

The impact of the field reduction effect on negative bias temperature instability (NBTI) parameter characterization and lifetime prediction was quantitatively studied in p-MOSFETs with a sub-1 nm equivalent oxide thickness (EOT). By comparing NBTI results under constant field stress and constant voltage stress, the field reduction effect was found to become severer at higher VG-STR and ${T}$ and cause a reduction in the voltage acceleration factor (VAF) at higher VG-STR and a reduction in activation energy EA at higher ${T}$ under constant voltage stress. To accurately evaluate NBTI lifetime, a modified NBTI model with field reduction correction (FRC) was proposed, and the 10-year NBTI degradation of a 32-stage ring oscillator was simulated. The results showed that the conventional model without including FRC had a worse prediction capability and overestimated frequency degradation for a ring oscillator. It is necessary to use an NBTI model with FRC for NBTI lifetime prediction of devices with a sub-1 nm EOT.

Method to extract parameters of power law for nano-scale SiON pMOSFETs under negative bias temperature instability

This paper proposes a fast and accurate method to extract parameters of the power law for nano-scale SiON pMOSFETs under negative bias temperature instability (NBTI), which is useful for an accurate estimation of NBTI lifetime. Experimental results show that accurate extraction of the time exponent n of the power law was obstructed by either fast trapping of minority carriers or damage recovery during measurement of threshold voltage Vth. These obstructing effects were eliminated using ΔVths obtained from fast and slow measurement-stress-measurement (MSM) procedures. The experimental SiON pMOSFETs had n ≈ 1/4, an activation energy Ea = 0.04 eV for the fast recoverable degradation, and Ea = 0.2 eV for the slow permanent degradation. Based on these experimental observations, a method to estimate NBTI lifetime is proposed.

Difference analysis method for negative bias temperature instability lifetime prediction in deeply scaled pMOSFETs

The fluctuation significantly affects the lifetime prediction of negative bias temperature instability (NBTI) for deeply scaled pMOSFETs. In this paper, we present a novel difference method to separate the time dependent fluctuation-related component from the NBTI quasi-static component in the threshold voltage shift. The extracted fluctuation-related component exhibits weak temperature and time dependences which is consistent with the characteristic of as-grown defect-induced trapping and detrapping while the quasi-static component presents electrical behaviors of generated-defect-induced NBTI degradation. On the basis of these results, a composite NBTI model is constructed and lifetime projection is derived for the small pMOSFETs.

Effect of Gate Oxide Thickness on Negative Bias Temperature Instability in p-Mosfet with Sion Gate Dielectrics

The major reliability issue of metal-oxide-semiconductor field-effect-transistor (MOSFET) had been mainly hot carrier injection (HCI) until the late 1990s. However, negative bias temperature instability (NBTI) has been focused on since late 1990s until now because both aggressive scaling-down of gate oxide thickness and nitrogen incorporation into gate oxide, which mitigate HCI, enhance NBTI severely [1-2]. Although the phenomenon of bias temperature instability (BTI) has been known for several decades, there is still no clear explanation regarding the roles of gate oxide thickness on NBTI degradation of p-MOSFETs. For example, N. Kimizuka et al. reported that NBTI lifetime in p-MOSFET with thin gate oxide is larger than that with thick gate oxide under equivalent oxide field stress in the range of 2.0 ~ 4.0 nm oxide thickness [3]. On the contrary, S. Mahapatra et al. reported that BTI could be enhanced in p-MOSFET with thinner gate oxide due to high diffusivity of H2 in gate poly [4]. Meanwhile, G. Pobegen et al. reported that NBTI were all the same in p-MOSFETs with gate oxide thickness of 5.6, 13.9 and 29.1 nm [5]. In this work, we tried to resolve conflicting experimental results reported in the literature: Since the reduction of gate oxide thickness will enhance electric field across gate oxide, the application of thinner gate oxide will deteriorate NBTI degradation such like threshold voltage shift (ΔVt) caused by charge generation. However, it also increases oxide capacitance, reducing the effect of generated positive charge which is one of the main sources for NBTI degradation. We fabricated p-MOSFET devices with SiON gate oxide and p+ poly-silicon gate stack in the commercial graded production line through conventional DRAM full processes. We evaluated p-MOSFETs with two different thicknesses of gate oxide: One is p-MOSFETs with thin gate oxide of 3.36 nm (‘thin PMOS’ hereafter), and the other is p-MOSFETs with gate oxide of 7.27 nm (‘thick PMOS’ hereafter). We evaluated NBTI degradation electrically by measuring the threshold voltage (Vt) before and after NBT stress for 1,000 seconds at 125 °C with Agilent 4156C. By means of stressing for 1,000 seconds without a break and by measuring just after stress, we could minimize undesirable variations caused by recovery. Data shown in Fig. 1(a) represent ΔVt caused by NBT stress of various gate voltages. In Fig. 1(a), the slope of ΔVt for thin PMOS devices is steeper than that of thick PMOS. However, if we redraw the same data of ΔVt as a function of oxide electric field (Eox), then we have the same ΔVtslope for both thin and thick PMOS devices regardless of gate oxide thickness, as shown in Fig. 1(b). NBTI has been known to be exponentially increased with oxide electric field [6], which expressed empirically as Eq. (1). Our NBTI data of both thin and thick PMOS have the identical B value of 0.69 cm/MV. Also, NBTI is generally known to be caused by both interface trap and positive oxide charge which were generated during the NBT stress [6]. The generated charges contribute to threshold voltage shift via Eq. (2). Therefore, the total increased charge density (ΔNtotal) can be written as Eq. (3). By using Eq. (3), the correlation between the increased trap density and the oxide field applied during the NBT stress test can be obtained from the data in Fig. 1(b), and the result is shown in Fig. 1(c), in which all data lay on the one straight line. This suggests that NBT stress with the equivalent oxide field causes the same amount of increased charges independent of gate oxide thickness. Therefore, Eq. (1) must be normalized by Coxto count this observation as Eq. (4). As shown in Fig. 2, it is remarkable that NBTI degradation becomes the minimum at the condition of Eq. (5). NBTI drops drastically down to the minimum point and then rises with the increase of gate oxide thickness, which accounts for the previous conflicting experimental results. In summary, we found that the total increased charge density of the devices subjected to NBT stress is same as long as the equivalent electric field is applied, regardless of gate oxide thickness. By modifying the empirical equation for ΔVt, we suggest that the optimal value of Tox can be selected for a given gate voltage and oxide field acceleration coefficient. This finding can be served as the new guideline on selecting gate voltage and gate oxide thickness to minimize the NBTI degradation both for process development and integrated circuit design. Figure 1

Technology Scaling Effect on the Relative Impact of NBTI and Process Variation on the Reliability of Digital Circuits

The impact of negative bias temperature instability (NBTI) on circuit reliability is typically assessed without accounting for the variability associated with the manufacturing process. With technology progression, manufacturing process variability scales more aggressively than transistor NBTI lifetime. Hence, a clear link between transistor and circuit reliability that takes variability into account is imperative to analyze circuit reliability. We propose a figure of merit termed fall-out to describe the proportion of circuits whose frequencies would exceed the initial manufacturing distribution. We use fall-out to assess NBTI and process variability in tandem, and we show that the fall-out of circuit frequency (or timing delay) peaks and diminishes as technology scales. We propose that the fall-out of a ring oscillator can be used as a worst-case indicator of circuit reliability in any given technology.

SiON Gate Dielectric Optimization for NBTI Improvement

Plasma nitride SiON films have been widely used as gate dielectric in advanced CMOS device fabrication since 90nm technology node. As a replacement material for conventional silicon dioxide, it can provide increased dielectric constant and serve as an effective boron barrier. Post nitridation anneal (PNA), a critical step for plasma nitride SiON formation, is used to stabilize plasma incorporated nitrogen radicals and ions through form thermal stable Si-N banding. Furthermore, PNA can repair the damaged Si/SiO2 interface by interface substrate re-oxidation under oxygen contained ambient. In this work, several PNA conditions were studied. Their effect on transistor performance and PMOS NBTI (Negative Bias Temperature Instability) lifetime were evaluated. It demonstrates that NBTI performance can be improved 20% by PNA process optimizing, while keeping the same Tinv thickness and Ioff/Ion performance.

Fluorine IMP Effect on Negative Bias Temperature Instability and Process Induced Defects

Negative Bias Temperature Instability (NBTI) is one of the major reliability concerns for pMOSFETs as the transistor gate oxide thickness is scaling down. Incorporating fluorine into the gate oxide is a well-known method to effectively suppress NBTI. The efficiency and mechanism are studied carefully in earlier reports. The focus of this paper is to analyze how the fluorine incorporation impacts on device performance and process integration. Different fluorine implantation conditions and their impacts on NBTI lifetime, device performance and process integration were studied and analyzed. The results demonstrated that fluorine implants could prolong pMOSFETs NBTI lifetime, but would reduce threshold voltage and degrade Ion-Ioff performance. Meanwhile, process defects were found if the F2 dose in the active area is greater than a certain value. Analysis and discussions are carried out to understand those phenomena.

NBTI Lifetime Prediction and Kinetics at Operation Bias Based on Ultrafast Pulse Measurement

Predicting negative bias temperature instability (NBTI) lifetime can be dangerous since it is difficult to assess its safety margin. The common technique uses gate bias V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> acceleration to reduce the test time, and the data were typically obtained from quasi-DC measurements. Recently, it has been shown that substantial recovery occurs during the quasi-DC measurement, and the suppression of recovery requires using ultrafast pulse measurement, where time was reduced to the order of microseconds. In a real circuit, different transistors have different levels of recovery, and the worst case scenario is when recovery is suppressed. At present, there is little information on how this worst case NBTI lifetime can be predicted and whether the traditional V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> acceleration technique can still be used. This work will show that the prediction based on the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> acceleration results in a substantial error, and its cause will be analyzed. To predict the worst case lifetime, a model for NBTI kinetics under operation gate bias is developed. This kinetics includes contributions from both as-grown and generated defects, and it no longer follows a simple power law. Based on the new kinetics, a single-test prediction method is proposed, and its safety margin is estimated to be 50%.

NBTI Reliability of P-Channel Transistors With Diamond-Like Carbon Liner Having Ultrahigh Compressive Stress

Negative bias temperature instability (NBTI) characteristics of p-channel field-effect transistors (p-FETs) with diamond-like carbon (DLC) liner stressor having ultrahigh compressive stress (~ 5 GPa) are investigated for the first time. Ultrafast measurement was employed for NBTI study. Power law slopes ranging from ~ 0.058 to ~ 0.072 are reported here. P-FETs with higher channel strain show greater threshold voltage shift (DeltaV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) and transconductance degradation than those with lower or no channel strain under the same NBT stress condition V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">stress</sub> . Strained p-FETs with Si S/D and DLC stressors are projected to have an NBTI lifetime of ten years at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = -0.99 V using E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> power law lifetime extrapolation model or at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = -0.76 V using the exponential V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">stress</sub> model.

Impact of Activation Annealing Temperature on the Performance, Negative Bias Temperature Instability, and Time-to-Dielectric Breakdown Lifetime of High-k/Metal Gate Stack p-Type Metal–Oxide–Semiconductor Field Effect Transistors

We have clarified the effects of activation annealing temperature on the negative bias temperature instability (NBTI) and time-dependent dielectric breakdown (TDDB) lifetime improvement of HfSiON/TiN gate stack p-type metal–oxide–semiconductor field effect transistors. Higher-temperature annealing is effective for the improvement in NBTI and TDDB lifetime. This is due to the Si substrate oxidation occuring during the high-temperature annealing, resulting in interface defect state reduction. Annealing is also effective for reducing threshold voltage with consequential improvement in device performance.

Effect of variable body bias technique on pMOSFET NBTI recovery

A study on the negative bias temperature instability (NBTI) recovery of a pMOSFET under variable body bias (VBB) is presented. The forward body bias enhanced NBTI recovery mechanism is proposed with evidence on the VBB dependency. Further, the influence of surface potential and the gate oxide electric field on the recovery indicated that the relaxation of the positive charge and interface trap played a different role in the NBTI recovery stage. It is shown that the forward VBB technique can achieve improvement in terms of drive capability and NBTI lifetime.

Accurate negative bias temperature instability lifetime prediction based on hole injection

Negative bias temperature instability (NBTI) lifetime prediction of thin gate insulator films based on hole injection without gate voltage acceleration is described and lifetime comparison between SiO 2 film and SiON film is made based on the prediction method. The acceleration parameters are most important for the accurate lifetime prediction. The proposed acceleration parameter is not the applied voltage to the gate insulator film and the temperature but quantity of the hole injection to the gate insulator film that directly relates with the quantity of holes in the inversion layer. The degradation mechanism under the excessive voltage and excessive temperature stresses are different from that in the operation conditions. Using the hole injection method, the NBTI lifetime of SiON is less than that of SiO 2. This result agrees with the reported results measured by conventional high gate fields and temperatures. By the introduction of effective stress time (= Q hole/ J inj0), accurate lifetime prediction in terms of the V th shift is realized, and by analyzing of relationship between I D reduction and V th shift, accurate lifetime prediction in terms of the I D reduction and the degradation prediction in the circuit level are realized. These results are essential for the accurate NBTI lifetime prediction for further more integrated LSI such as very thin gate insulator films around 1 nm.

Investigation of Reliability Characteristics in NMOS and PMOS FinFETs

Three-dimensional vertical double-gate (FinFET) devices with a high aspect ratio (Si-fin height/width = H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> /W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> = 86 nm/17 nm) and a gate nitrided oxide of 14 Aring thickness have been successfully fabricated. Reliability characterizations, including hot-carrier injection (HCI) for NMOS FinFETs and negative bias temperature instability (NBTI) for PMOS FinFETs, are carried out in order to determine their respective lifetimes. The predicted HCI dc lifetime for a 50-nm gate-length NMOS FinFET device at the normal operating voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cc</sub> ) of 1.1 V is 133 years. A wider fin-width (27 nm) PMOS FinFET exhibits promising NBTI lifetime such as 26.84 years operating at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cc</sub> = 1.1 V, whereas lifetime is degraded for a narrower fin-width (17 nm) device that yields 2.76 years of lifetime at the same operating voltage and stress conditions.