Investigation of Reliability Characteristics in NMOS and PMOS FinFETs

Abstract

Three-dimensional vertical double-gate (FinFET) devices with a high aspect ratio (Si-fin height/width = H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> /W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> = 86 nm/17 nm) and a gate nitrided oxide of 14 Aring thickness have been successfully fabricated. Reliability characterizations, including hot-carrier injection (HCI) for NMOS FinFETs and negative bias temperature instability (NBTI) for PMOS FinFETs, are carried out in order to determine their respective lifetimes. The predicted HCI dc lifetime for a 50-nm gate-length NMOS FinFET device at the normal operating voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cc</sub> ) of 1.1 V is 133 years. A wider fin-width (27 nm) PMOS FinFET exhibits promising NBTI lifetime such as 26.84 years operating at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cc</sub> = 1.1 V, whereas lifetime is degraded for a narrower fin-width (17 nm) device that yields 2.76 years of lifetime at the same operating voltage and stress conditions.