Abstract
The method of fluorine implant directly after a poly gate deposition process step is proposed to improve both electrical characteristics and reliabilities by creating Si-F bonding at a gate oxide interface and negative fixed charged in a gate oxide. Capacitance-voltage (C-V) curve and gate oxide leakage current was used to investigate oxide thickness and flat band voltage (Vfb) shift. Experimental results show fluorine implant induced regrowth of gate oxide ~1 Å and Vfb shift ~−40 mV. Owing to the Vfb shift, ~24 mV of drain induced barrier lowering is improved. Furthermore, gate oxide interface quality was evaluated using charge pumping current and negative bias temperature instability (NBTI), and gate oxide quality was evaluated using time-dependent dielectric breakdown (TDDB). The results show that the fluorine implant process which is prosed in this paper reduced 27% of the interface trap and improved ~0.8 order higher NBTI lifetime. TDDB lifetime showed a slight improvement when using the proposed method. Thus, a controlled fluorine implant step improves both DC electrical characteristics and gate oxide reliabilities. These suggest that the fluorine implant step should be carefully selected when fabricating PMOSFETs.
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