Nanowire Tunnel Field Effect Research Articles

Charge Plasma Based Si1-xGex Sourced Nanowire Tunnel Field Effect Transistor Oxygen Gas Device with Enhanced Sensitivity

Charge Plasma Based Si1-xGex Sourced Nanowire Tunnel Field Effect Transistor Oxygen Gas Device with Enhanced Sensitivity

An Improved Structure and Analysis of Asymmetrical Spacer Nanowire Tunnel Field Effect Transistor

An Improved Structure and Analysis of Asymmetrical Spacer Nanowire Tunnel Field Effect Transistor

Design and Analysis of Junctionless-Based Gate All Around N+ Doped Layer Nanowire TFET Biosensor

This work is based on the analysis and designing of Gate All Around N+ doped layer Nanowire Tunnel Field Effect Transistors (NTFET) without junctions for application in biosensor by considering the various bio molecules like uricase, proteins, biotin, streptavidin, Aminopropyl-triethoxy-silane (ATS) and many more with dielectric modulation technique and gate-all-around (GAA) environment. Device sensitivity and tunneling probability is further improved by N+ doped layer (1 × 1020 cm−3). The change in the subthreshold-slope (SS), drain current (ID), transconductance(gm), and ratio of ION/IOFF has been examined to detect the sensitivity of the proposed device by confining various biomolecules in the area of nanocavity. The nanocavity area creates a shield in the source gate of oxide layer and electrodes metal. The Junctionless Gate All Around Nanowire Tunnel-Field-Effect-Transistor (JLGAA-NTFET) shows less leakage current and large control on the channel. The design of JLGAA-NTFET is with high doping concentration and observed higher sensitivity for ATS biomolecule which is suitable for sensor design application.

Design and optimization of vertical nanowire tunnel FET with electrostatic doping

While dealing with the nanoscale regime, most devices make sacrifices in terms of performance. So to meet the performance requirements, Electrostatic doped Vertical Nanowire Tunnel Field Effect Transistor (E-VNWTFET) is proposed and analysed in this work. The dimensions of Electrostatic VNWTFET structure are scaled down and then the analog performance parameters transconductance gm, gm2 (2nd order), gm3 (3rd order) and linearity parameters 2nd order Voltage Interception Point VIP2, 3rd order Voltage Interception Point VIP3, 3rd order Input Interception Point IIP3 and 3rd order Intermodulation Distortion IMD3 are analysed. It is observed that electrostatic technique of doping is better than charge plasma (CP) technique; because in CP technique costly metals are required for doping. The analog performance parameters of E-VNWTFET are investigated and using device simulation the demonstrated characteristics are compared with CP-VNWTFET. After simulation, the device exhibits ON current ION of 3.5 μA μm−1 and OFF current IOFF of 6.6 × 10−18 A μm−1; which offers a significant ION/IOFF of 1011. The reported subthreshold swing and Drain-induced barrier lowering DIBL are approx. 9.7 mV/Decade and 37.8 mV/V respectively.

Design of Si0.5Ge0.5 Sourced Nano-cantilever Pressure Sensor Based on Charge Plasma and Gate Stacked Nanowire Tunnel Field Effect Transistor

Design of Si0.5Ge0.5 Sourced Nano-cantilever Pressure Sensor Based on Charge Plasma and Gate Stacked Nanowire Tunnel Field Effect Transistor

Design and simulation of junctionless nanowire tunnel field effect transistor for highly sensitive biosensor

This paper investigates symmetrical design of a Junctionless Nanowire Tunnel-Field-Effect-Transistor (JL-NWTFET) for highly sensitive biosensor. JL-NWTFET deployed using Gate-All-Around (GAA) structure and Dielectric-Modulation (DM) technique to detects the bio-logical molecules such as uricase, streptavidin, protein, biotin, uriease, Amino-propyl triethoxysilane (APTS), ChOx etc. The variation in the drain current (ID), subthreshold slope (SS), transconductance (gm), and ION/IOFF ratio considered as the sensitivity parameters of the JL-NWTFET to detect different biological molecules in the cavity area. The cavity area is formed by a layer in between the source-gate oxides and source-gate electrodes. The JL-NWTFET shows the reduced leakage currents in terms of Short-Channel-Effects (SCEs) and superior controllability over the channel. The proposed JL-NWTFET has been designed with uniform doping concentration (1 × 10−19 cm−3), and gate work-function (φgate = 4.8eV). The high sensitivity (∼109) is observed for APTS biomolecule with dielectric constant (K = 3.57).

Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis

This work presents the comparison between Nanowire Tunnel Field-Effect Transistor (NW-TFET) and Line-TFET applied on the design of Low-Dropout Voltage Regulator (LDO). Both devices have a SiGe source composition in order to enhance the current drive. The transistors were modeled using lookup tables (LUTs) approach based on experimental data using Verilog-A language. The LDOs were designed for two conditions, considering different gm/ID, load currents and load capacitances. In order to compare the TFET LDOs with an established technology, a MOSFET LDO was designed with TSMC 0.18 µm process design kit. Both TFET LDOs reach stability without the presence of a compensation capacitor. For gm/ID = 10.5 V−1 the current consumption of NW-TFET LDO (1.5nA) is near two orders of magnitude lower than Line-TFET LDO (68nA) and three orders of magnitude lower than MOSFET LDO (9 µA). The Line-TFET LDO exhibits better results in almost all parameters despite of the gain-bandwidth product (GBW) that is in the same order of magnitude of the MOSFET LDO, 171 kHz compared to 250 kHz for gm/ID = 10.5 V−1. The comparison between TFET LDOs for gm/ID = 7 V−1 was also performed regarding the transient and process variability analysis. The transient response revealed that the Line-TFET LDO has a pronounced lower settling time, 71 µs compared to 5 ms for a load step, but with a damped oscillatory response, the NW-TFET LDO presented lower undershoot for the load step. The process variability analysis was performed for devices within the wafer and was observed that the Line-TFET LDO suffers a higher impact with a 20 dB variation on the loop gain in comparison to 10 dB in the NW-TFET LDO.

Design and performance analysis of gate-all-around negative capacitance dopingless nanowire tunnel field effect transistor

In this paper, a novel low power consumption device based on a dopingless gate-all-around nanowire tunnel field effect transistor (TFET) with negative capacitance (NC) effect is proposed. NC is a robust approach in solving the bottleneck issues encountered by devices operating in nanoscale domains. Additionally, the threshold voltage (V T) and subthreshold swing (SS) are dropped significantly to less than 60 mV/decade. Negative capacitance makes a significant contribution to the device’s performance by lowering the operating voltage for low-power applications. To calculate the optimum bias, the Landau–Khalatnikov (L–K) equation was used. To evaluate the influence of NC, the ferroelectric (FE) material PZT (lead zirconate titanate), which has perovskite properties, was used as a gate insulator. Thus, the gate-all-around dopingless nanowire TFET (GAA DL NW TFET) device structure is reconfigured into GAA NC DL NW TFET. PZT has an appropriate polarization rate, high dielectric capacitance, and a high degree of reliability. To achieve an SS lower than 60 mV/decade at lower V T, effective tuning of the FE thickness is critical to avoid hysteresis, which enhances the overall performance of the proposed device. The aggressively scaled device has the problem of fabrication complexity and its associated cost that is addressed with the help of the dopingless technique to the nanowire-based TFET. The enhancement of the ON-current with an improved steep SS was addressed. With the application of the NC technique, the proposed device showcased an improved 4 µA µm−1 of I ON, and 1012 of current ratio. Additionally, the influence of the variation in FE thickness on the performance parameters is examined. The proposed device structure operates at a minimum operating voltage, making it an ideal choice for low-power voltage applications.

Investigation of variation in temperature on steep subthreshold slope nanowire tunnel field effect transistor based biosensor

Biosensors are critical part of today’s lifestyle. They have vast applications in medical industries making continuous advancement in the domain crucial. To further extend their utilities in this manuscript effect of variation in temperature on charge plasma based tunnel field effect transistor as biosensor is investigated. To investigate, device is simulated at 200 K, 300 K and 400 K and various device, analog and linearity characteristics are examined. To create the cavity for accommodation of biomolecules, source electrode is extended. Analyzed device resulted in steepest subthreshold slope of 17.61mV dec−1 and 8.81mV dec−1 for κ = 3 at T = 200 K. Device also has high ION sensitivity for entire temperature range. Due to promising characteristics, investigated biosensor can be used in future for detection of different biomolecules.

Comparative Analysis of Nanowire Tunnel Field Effect Transistor for Low Power Application

Comparative Analysis of Nanowire Tunnel Field Effect Transistor for Low Power Application

Comparison between low-dropout voltage regulators designed with line and nanowire tunnel field effect transistors using experimental data

This paper presents the comparison of Low-Dropout Voltage Regulators (LDOs) designed with Nanowire (NW-TFET) and Line Tunnel FET (Line-TFET), in which the transistors were modeled using Verilog-A and Lookup Tables (LUTs) obtained from experimental data. The LDOs were designed in two gm/ID, load currents and capacitances conditions: 7 V−1, 100 µA, 100 pF and 10.5 V−1, 10 µA, 10 pF. For comparison, a MOSFET LDO was designed with TSCM 0.18 µm PDK. It was observed that both TFET LDOs can be designed without the compensation capacitor to reach stability. The Line-TFET LDO delivers better specifications than the NW-TFET LDO, but with higher current consumption. Comparing with MOSFET LDO, both TFET LDOs present higher efficiency. The Line-TFET LDO showed higher loop gain and lower, but comparable, gain-bandwidth product (GBW) in both biases.

Charge Plasma Based Vertical Nanowire Tunnel Field Effect Transistor: Design and Sensitivity Analysis for Biosensing Application

Charge Plasma Based Vertical Nanowire Tunnel Field Effect Transistor: Design and Sensitivity Analysis for Biosensing Application

Parametric Investigation and Design of Junctionless Nanowire Tunnel Field Effect Transistor

Parametric Investigation and Design of Junctionless Nanowire Tunnel Field Effect Transistor

Design and Performance Enhancement of Gate-on-Source PNPN Doping–Less Vertical Nanowire TFET

This paper outlines the study of a Doping-Less Vertical Nanowire Tunnel Field Effect Transistor (DLVNWTFET) with a p-i-n structure, aiming to enhance the performance of this device. The proposed device, which is a p-n-p-n configured DLVNWTFET, switches with a steeper sub-threshold slope while keeping the Off-state current (IOFF) and threshold-voltage (VTH) low and also improves the On-state current (ION) of the device; which is one of the crucial problems in TFETs. The nanowire TFET structure is vertically grown on an intrinsic silicon wafer. This vertical structure eases the fabrication process and also helps in the implementation of Charge-Plasma (CP) Technique. It is a process by which electrodes of specific work functions are used to induce charges in the Source (P) and Drain (N) regions. To realize the p-n-p-n configured structure, pocketing technique is used where the N + heavily doped pocket is introduced between the Source and the Channel through CP concept. Upon calculation and comparison of various analog and device parameters, the proposed p-n-p-n structure shows better performance in contrast to the p-i-n DLVNWTFET. Analysis of the performance of the two configurations has been done, comparing various parameters like transconductance (Gm), output conductance (GD), transfer characteristics (ID–VGS), output characteristics (ID–VDS), cut-off frequency (fT), total gate capacitance (CGG) and intrinsic gain.

Electrical characterization of si nanowire GAA-TFET based on dimensions downscaling

This research paper explains the effect of the dimensions of Gate-all-around Si nanowire tunneling field effect transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (VT). These parameters are critical factors of the characteristics of tunnel field effect transistors. The Silvaco TCAD has been used to study the electrical characteristics of Si-NW TFET. Output (gate voltage-drain current) characteristics with channel dimensions were simulated. Results show that 50nm long nanowires with 9nm-18nm diameter and 3nm oxide thickness tend to have the best nanowire tunnel field effect transistor (Si-NW TFET) characteristics.

Design analysis of Gate-All-Around nanowire tunnel field effect transistor

In this paper the effect of physical design parameters on electrical characteristics of cylindrical tunnel field effect transistor has been studied by a numerical simulator. Simulations are performed on technology node varied from 40 nm to 20 nm based on which the results have been extracted at an optimized 30 nm channel length by employing different substrate material with assorted gate oxide material. Deviation in transfer characteristics have also been observed by varying thickness of gate oxide and work function of gate. Comparisons of different materials with oxides brought out nitride with silicon as the better combination, with ON current of about 1µA/µm and OFF current less than 1 pA/µm. This work gives an understanding of the involvement of physical parameters in the operation of the device.

Nanowire Tunnel Field Effect Transistors at High Temperature

The aim of this work is to study how the performance of nanowire tunnel field effect transistors (TFETs) is influenced by temperature variation. First of all, simulated energy band diagrams were presented to justify its fundamental working principle and this analysis was compared to experimental data obtained for temperature ranging from 300 to 420 K. This methodology was performed for different nanowire diameters and bias conditions, leading to a deep investigation of parameters such as the ratio of on-state and off-state current (ION/IOFF) and the subthreshold slope (S). Three different transport mechanisms (band-to-band tunneling, Shockley-Read-Hall generation/recombination and trap-assisted tunneling) were highlighted to explain the temperature influence on the drain current. As the final step, subthreshold slope values for each configuration were compared to the room temperature. Therefore, it was observed that larger nanowire diameters and lower temperatures tended to increase ION/IOFF ratio. Meanwhile, it was clear that band-to-band tunneling prevailed for higher gate voltage bias, resulting in a much slighter temperature effect on the drain current.

Comparative Analysis of Nanowire Tunnel Field Effect Transistor for Biosensor Applications

Nanowire based devices are most important candidate for future generation application. The unique advantage of Nanowire as a channel material is one dimensional conduction, low subthreshold leakage current as well high electron mobility. Moreover Nanowire posses unique prosperities such as chemical, optical, electrical and mechanical making them suitable for sensor design. Nanowire Tunnel Field Effect Transistor (NW-TFET) has potential bio-sensor applications as ultra-low power highly sensitive sensors alternative to conventional sensors. NW-TFET can offer sharp inverse subthreshold slope (SS) leads to low leakage current. The important working mechanism is band-to-band tunnelling (BTBT) in TFET and their structures are based on gate-all-around (GAA). This paper presents, recent advancements made on process, purpose and properties of NW-TFET and comparison on various NW-TFET structures and their characteristics. Various categories include in this paper are GAA, Junctionless, hetrojunction, charge plasma, doppingless, or in combination with multigate work functions are discussed. The comparative study revealed that HT-JL-DG-NW-TFET outperforms and highly sensitive bio-sensor application and better device performance over other NW-TFET.

Novel Asymmetric Recessed-Gate/Source Architecture Advancement of Dual-Metal-Gate SiGe/Si Dopingless Nanowire-TFET for Low-Voltage Performance Optimization

A dopingless vertical Nanowire (NW) Tunnel Field Effect Transistor TFET structure has been designed using techniques such as Dual-Metal Gate (DMG), Heteromaterial Channel (HmC) and Heterodielectric Oxide (HdO) to enhance the device performance. The proposed device is investigated to acknowledge the device behavior for RF/Low-Noise applications. The essence of the reported work is to capture the effect of work function variation of DMG on device characteristics for noise enhancement/degradation. The vertical structure simplifies the implementation of charge-plasma technique for induced doping within the source/drain region enveloped by Gate-All-Around (GAA) architecture. Different work function combinations of gate metal1 (GM1) and gate metal2 (GM2) are used for calculations and compared to acquire optimized results. Other than Silicon, Silicon-Germanium compound (SixGe1-x) with composition factor (x) equals to 0.55 is used for HmC, whereas Zirconium Silicate is preferred for HdO. The characteristics analysis includes the negative drain bias variation that captures an interesting tunnel diode characteristics with peak current to valley current ratio of approx. 108. The proposed structure is modified to reduce the Gate-to-Source capacitive coupling and drain current enhancement. The proposed device is analyzed for Ambipolar-state, OFF-state and ON-state, which is required to understand the proper working of TFET devices.

Operational transconductance amplifier designed with nanowire tunnel-FET with Si, SiGe and Ge sources using experimental data

In this paper operational transconductance amplifiers (OTA) were designed with nanowire (NW) tunnel field effect transistors (TFET) with different source materials (Si, SiGe, and Ge) and compared with NW Si MOSFET devices. Lookup tables with experimental data were used to model the transistors and simulate the OTAs. At the same dimensions and transistor efficiency region, the TFET OTAs have larger gain than the MOSFET circuit. The Ge-source TFET OTA presents the highest differential gain (105 dB), followed by the Si TFET (96 dB) and the SiGe-source TFET (90 dB), with the MOSFET presenting the lowest gain (51 dB). However, the MOSFET has the best gain-bandwidth product (GBW) (9.2 MHz) followed by the Ge-source TFET (1.6 MHz), the SiGe-source TFET (900 kHz) and the Si TFET (41 kHz). The second group of OTAs, where the same power consumption was considered and where the gain of the MOSFET OTA and the GBW of the TFETs’ circuits were increased was also studied. The gain of the MOSFET OTA increased to 56 dB, but it is still lower than the TFET circuits (96, 90 and 102 dB for the Si TFET, SiGe-source TFET and Ge-source TFET, respectively). The GBW of the Si TFET, SiGe-source TFET and Ge-source TFET circuits increased to 71 kHz, 1 MHz, and 2 MHz, respectively. Nevertheless, the MOSFET OTA has the best GBW (4.7 MHz) again but being just 2.35 times the GBW of the Ge-source TFET case. Therefore, because of the high gain of the TFETs OTAs, they are indicated for low power, low-frequency applications, with the Ge-source TFET presenting a good compromise between gain and GBW. The circuits’ linearity was also verified, and they demonstrate to be more dependent on bias choices than on the devices themselves.