Abstract
This paper outlines the study of a Doping-Less Vertical Nanowire Tunnel Field Effect Transistor (DLVNWTFET) with a p-i-n structure, aiming to enhance the performance of this device. The proposed device, which is a p-n-p-n configured DLVNWTFET, switches with a steeper sub-threshold slope while keeping the Off-state current (IOFF) and threshold-voltage (VTH) low and also improves the On-state current (ION) of the device; which is one of the crucial problems in TFETs. The nanowire TFET structure is vertically grown on an intrinsic silicon wafer. This vertical structure eases the fabrication process and also helps in the implementation of Charge-Plasma (CP) Technique. It is a process by which electrodes of specific work functions are used to induce charges in the Source (P) and Drain (N) regions. To realize the p-n-p-n configured structure, pocketing technique is used where the N + heavily doped pocket is introduced between the Source and the Channel through CP concept. Upon calculation and comparison of various analog and device parameters, the proposed p-n-p-n structure shows better performance in contrast to the p-i-n DLVNWTFET. Analysis of the performance of the two configurations has been done, comparing various parameters like transconductance (Gm), output conductance (GD), transfer characteristics (ID–VGS), output characteristics (ID–VDS), cut-off frequency (fT), total gate capacitance (CGG) and intrinsic gain.
Highlights
The electronics industry has been greatly influenced since the remarkable technological invention of Integrated Circuits
This paper outlines the study of a Doping-Less Vertical Nanowire Tunnel Field Effect Transistor (DLVNWTFET) with a p-i-n structure, aiming to enhance the performance of this device
In 1965, Moore predicted the pace of upcoming revolution in modern digital era, which became the golden rule for electronics industry
Summary
The electronics industry has been greatly influenced since the remarkable technological invention of Integrated Circuits. TFETs have shown potential to be considered as a capable alternative as they outperform MOSFET in terms of SS, VTH and IOFF [5] This is made possible due to the mechanism of TFET i.e., Band to Band Tunnelling, which increases the On to Off State Current ratio (ION/IOFF) as compared to Thermionic emission in MOSFET. This breaks the limitation of MOSFET by achieving a SS lower than 60 mv/dec. The objective is to achieve high Ion, low VT, reduce cost and overcome the shortcomings of Conventional TFETs. in this paper, a Doping-Less Vertical Nanowire Tunnel Field Effect Transistor is being introduced which has a p-n-p-n configuration. The p-n-p-n configured structure is similar to the p-i-n TFETS with a variation by introducing a n-pocket from the CP technique
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
