Design and performance analysis of gate-all-around negative capacitance dopingless nanowire tunnel field effect transistor

Abstract

In this paper, a novel low power consumption device based on a dopingless gate-all-around nanowire tunnel field effect transistor (TFET) with negative capacitance (NC) effect is proposed. NC is a robust approach in solving the bottleneck issues encountered by devices operating in nanoscale domains. Additionally, the threshold voltage (V T) and subthreshold swing (SS) are dropped significantly to less than 60 mV/decade. Negative capacitance makes a significant contribution to the device’s performance by lowering the operating voltage for low-power applications. To calculate the optimum bias, the Landau–Khalatnikov (L–K) equation was used. To evaluate the influence of NC, the ferroelectric (FE) material PZT (lead zirconate titanate), which has perovskite properties, was used as a gate insulator. Thus, the gate-all-around dopingless nanowire TFET (GAA DL NW TFET) device structure is reconfigured into GAA NC DL NW TFET. PZT has an appropriate polarization rate, high dielectric capacitance, and a high degree of reliability. To achieve an SS lower than 60 mV/decade at lower V T, effective tuning of the FE thickness is critical to avoid hysteresis, which enhances the overall performance of the proposed device. The aggressively scaled device has the problem of fabrication complexity and its associated cost that is addressed with the help of the dopingless technique to the nanowire-based TFET. The enhancement of the ON-current with an improved steep SS was addressed. With the application of the NC technique, the proposed device showcased an improved 4 µA µm−1 of I ON, and 1012 of current ratio. Additionally, the influence of the variation in FE thickness on the performance parameters is examined. The proposed device structure operates at a minimum operating voltage, making it an ideal choice for low-power voltage applications.