N-metal Oxide Semiconductor Field Effect Research Articles

Work Function Estimation of Gallium-Doped Zinc Oxide Using Transparent Gate Electrode MOSFET

In this research, the work function (WF) of RF sputtered GZO thin films has been estimated using the electrical characteristics n-Metal Oxide Semiconductor Field Effect Transistor (n-MOSFET) device. Two identical sets of MOSFETs were fabricated in this work using a four-level mask. These MOSFETs have two different types of gate contact materials (Al and GZO respectively). GZO was deposited by using RF magnetron sputtering technique while Al was deposited using the thermal evaporation technique. By comparison of the work function of the two MOSFETs, the work function of RF sputtered GZO thin films was identified to be around 4.58 eV.

Work Function Extraction of Transparent Conducting Indium Oxide Films Used As Gate Electrode for MOSFET

Indium Oxide (In2O3) has received a great deal of attention recently as a transparent conducting oxide (TCO) semiconductor that finds applications in photovoltaic solar cells, transparent windows [1] and flat panel displays due to its high electrical conductivity and good optical transparency in the visible region [2]. It is critical to understand the work function (WF) of a material since it is an important characteristic which has an impact on the device performance.In this work, WF of In2O3 has been estimated by fabricating n-Metal Oxide Semiconductor Field Effect Transistor (NMOSFET). Fabrication of two MOSFET devices has been carried out using four-level mask. The source and drain contacts for both the devices have been prepared by using Aluminum metal. The gate contact for one of the MOSFET devices was prepared using Aluminum metal and transparent conducting In2O3 is used as the gate contact for the second MOSFET. Aluminum deposition was carried out using thermal evaporation technique. A 2-inch copper-backed indium target is used to deposit thin films of In2O3 by RF magnetron sputtering and varying the oxygen gas flow. The substrate temperature is held constant at room temperature. Electrical characterization is performed on the fabricated MOSFETs which is further used in extracting the WF of In2O3 thin films. Timo Jäger, Yaroslav E. Romanyuk, Shiro Nishiwaki, Benjamin Bissig, Fabian Pianezzi, Peter Fuchs, Christina Gretener, Max Döbeli, and Ayodhya N. Tiwari , "Hydrogenated indium oxide window layers for high-efficiency Cu(In,Ga)Se2 solar cells" , Journal of Applied Physics 117, 205301 (2015)Min-Suk Lee, Won Chel Choi, Eun Kyu Kim, Chun Keun Kim, Suk-Ki Min, Characterization of the oxidized indium thin films with thermal oxidation, Thin Solid Films, Volume 279, Issues 1–2, 1996, Pages 1-3, ISSN 0040-6090.

Work Function Extraction of Transparent Conducting Indium Oxide Films Used As Gate Electrode for MOSFET

In this work, work function of In2O3 has been estimated by fabricating n-Metal Oxide Semiconductor Field Effect Transistor (n-MOSFET) device. Two types of MOSFET devices has been fabricated using a four-level mask. Aluminum (Al) deposited using thermal evaporation was used as the gate contact for one type of MOSFET whereas transparent conducting In2O3 fabricated using RF magnetron sputtering technique was used as the gate contact metal for the second type of MOSFET. Work function of In2O3 was extracted by electrical characterization of the MOSFET devices. The average work function of In2O3 thin films was calculated to be 4.21 eV.

The Impacts of Contact Etch Stop Layer Thickness and Gate Height on Channel Stress in Strained N-Metal Oxide Semiconductor Field Effect Transistors.

The stress induced by strain in the channel of metal oxide semiconductor field effect transistors (MOSFET) is an effective method to boost the device performance. The geometric dimensions of spacer, gate height, and the contact etch stop layer (CESL) are important factors among the feasible booster. This study utilized the mismatch of the thermal expansion coefficients of stressors to simulate the process-induced stress in the N-MOSFET. Different temperatures are applied to different region of the device to generate the required strain. The analysis was performed by well-developed finite element package. The composite spacers with variant width of inserted silicon nitride (SiO2/SiN/SiO2, ONO) were proposed and their impacts on channel stress were compared. Two aspects of the impacts of those factors on the channel stress in the longitudinal direction for N-MOSFET with variant channel length were investigated. Firstly, the channel stresses of device without CESL for different gate heights were studied. Secondly, with stress applied to CESL and ONO spacers, the induced stresses in the channel were analyzed for long/short gate length. Two conclusions were drawn from the results of simulation. The N-MOSFET device without CESL shows that the stressed spacer alone generates compressive stress and the magnitude increases along with higher gate height. The channel stress becomes tensile for device with CESL and increases when the thickness of CESL and the height of gate increase, especially for device with shorter gate length. The gate height plays more significant role in inducing channel stress compared with the thickness of CESL. The channel stress can be used to quantify the mobility of electron/hole for strained MOSFET device. Therefore, with the guideline disclosed in this study, better device performance can be expected for N-MOSFET.

Carbon Incorporation into Substitutional Silicon Site by Molecular Carbon Ion Implantation and Recrystallization Annealing as Stress Technique in n-Metal–Oxide–Semiconductor Field-Effect Transistor

Since the lattice constant of silicon-carbon (Si:C) is smaller than that of Si, Si:C embedded in the source and drain (e-Si:C S/D) can induce tensile stress in the channel and improve the electron mobility of n-metal–oxide–semiconductor field-effect transistor (nMOSFETs). In this research, molecular carbon (C) ion implantation and recrystallization schemes employed to achieve strained Si:C films with a high substitutionally incorporated carbon concentration ([C]sub) and a high ratio of substitution were studied. Several recrystallization techniques including rapid-thermal-annealing (RTA)-based solid phase epitaxy (SPE), spike annealing, and nonmelt laser annealing have been used to optimize C incorporation into Si and strain application. Results of these different implantation and annealing techniques are compared and discussed. Furthermore, we proposed the first recrystallization by nonmelt laser annealing and the co-incorporation of a dopant that increases the rate of Si regrowth and has a covalent radius slightly different from that of Si. These processes markedly promoted the recrystallization of C densely incorporated in an amorphous Si layer and improved the crystallinity of strained Si:C films while maintaining a high [C]sub at a high ratio of substitution.

Effect of nitrogen implantation at the SiO2/SiC interface on the electron mobility and free carrier density in 4H-SiC metal oxide semiconductor field effect transistor channel

The electrical characteristics of n-metal oxide semiconductor field effect transistors (n-MOSFETs) fabricated on 4H-SiC with a process based on nitrogen (N) implantation in the channel region before the growth of the gate oxide are reported as a function of the N concentration at the SiO2/SiC interface. A strong correlation among the increase in the N concentration, the reduction of the interface state density near the conduction band and the improvement of the MOSFET performance was obtained. Hall-effect measurements were used to determine the electron mobility and the free carrier concentration in the MOSFET channel. Among the investigated combinations of N dose and oxidation time, the one with the higher dose and the shorter time produces MOSFETs with the higher N concentration at the SiO2/SiC interface and the best electrical characteristics. This superior performance is obtained in spite of the lowering of the bulk mobility in the channel of this sample, a negative effect probably ascribable to the incomplete recovery of the implantation damage or to the high density of interstitial nitrogen atoms present in the channel region. However, evidence of extended defects, clusters or nanoparticles was not observed by transmission electron microscopy analyses in any of the investigated SiC MOSFET devices.

Atomically-Engineered Interfaces Between Crystalline-Ge Substrates and i) Nanocrystalline HfO2 and ii) Non-Crystalline Hf Si Oxynitride High-K Dielectrics

This paper presents a spectroscopic study of interfacial bonding and substrate gate dielectric reactions for crystalline Ge-high-K gate dielectric hetero-structures. A novel processing sequence has been developed for i) depositing HfO2 and Hf Si oxynitrides (HfSiON) onto N-passivated Ge(111) and (100) substrates in an attempt to prevent subcutaneous oxidation of the Ge substrate during dielectric deposition, and then ii) eliminating these Ge-N interfacial bonds during 650-800°C rapid thermal annealing in Ar. This approach has been motivated by previous spectroscopic studies which have demonstrated that the band-gaps of GeO2 and Ge3N4 are reduced with respect to their Si counterparts, and cannot be used as interfacial layers (ILs) on n-type Ge substrates, or in n-metal oxide semiconductor field effect transistors (n-MOSFETs) in which a p-type Ge substrate has been inverted. Changes in interface bonding as a function of post-deposition annealing for Ge/HfO2 and HfSiON, and HfO2/HfSiON stacks have been studied by X-ray absorption and photoelectron spectroscopies, revealing i) intrinsic, or pre-existing conduction and valence band edge defects, and ii) process-induced changes in band edge defects as well. [DOI: 10.1380/ejssnt.2009.381]

Reduced Pressure–Chemical Vapour Deposition of Si/SiGe heterostructures for nanoelectronics

We have first of all quantified the impact of pressure on Si and SiGe growth kinetics. Definite growth rate and Ge concentration increases with the pressure have been evidenced at low temperatures (650–750 °C). By contrast, the high temperature (950–1050 °C) Si growth rate either increases or decreases with pressure (gaseous precursor depending). We have then described the selective epitaxial growth process we use to form Si or Si 0.7Ge 0.3:B raised sources and drains on ultra-thin patterned Silicon-On-Insulator (SOI) substrates. We have afterwards presented the specifics of SiGe virtual substrates and of the tensile-strained Si layers grown on top (used as templates for the elaboration of tensily strained-SOI wafers). The tensile strain, which can be tailored from 1.3 up to 3 GPa, leads to an electron mobility gain by a factor of 2 in n-Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) built on top. High Ge content SiGe virtual substrates can also be used for the elaboration of compressively strained Ge channels, with impressive hole mobility gains (×9) compared to bulk Si. After that, we have described the main structural features of thick Ge layers grown directly on Si (that can be used as donor wafers for the elaboration of GeOI wafers or as the active medium of near infrared photo-detectors). Finally, we have shown how Si/SiGe multilayers can be used for the formation of high performance 3D devices such as multi-bridge channel or nano-beam gate-all-around FETs, the SiGe sacrificial layers being removed thanks to plasma dry etching, wet etching or in situ gaseous HCl etching.

Dependence of Electrical Characteristics on Si Thickness and Ge Concentration for Unstrained Si Grown on Strained SiGe-on-Insulator n-Metal–Oxide–Semiconductor Field-Effect Transistor

The dependencies of the electrical characteristics of n-metal–oxide–semiconductor field-effect transistors (n-MOSFETs) on the nano-scale Si thickness (<20 nm) and Ge concentration for unstrained Si grown on strained SiGe-on-insulator were investigated. As the Si thickness decreased, the electron mobility decreased more significantly than the strained Si n-MOSFET grown on relaxed SiGe-on-insulator (SGOI). In addition, the electron mobility decreased with increasing the Ge concentration, contrary to strained Si SGOI n-MOSFET.

Electrical Characterization of 256 Mbit DRAM with Carbon-Implanted Drain

In this paper, we report a carbon-implanted drain on the contact to bitline per cell transistor investigated for 0.14 μm dynamic random access memory (DRAM) generation. It is found that an n-metal oxide semiconductor field effect transistor (n-MOSFET) with a carbon-implanted drain can promote a 7% improvement of production yield of a 256 Mbit DRAM. This technique exhibits excellent electrical properties such as threshold voltage, drive current, and bit contact resistance. This indicates that the presence of carbon suppresses transient enhanced diffusion and dislocation formation generated by other implant species.

Drive Current Enhancement in Sub-50 nm CMOS by Reduction of SDE Resistance with Laser Thermal Process

In this paper, we report on the ultrashallow junction profiles and good characteristics of sub-50 nm bulk complementary metal oxide semiconductor (CMOS) devices with n+/p+ source-drain extensions (SDEs) formed by laser thermal processing (LTP). By combining LTP with preamorphization and strong-dosage dopant-ion implantation, CMOS drive current can be improved without incurring a cost in terms of short-channel deterioration. The SDE-junction depth, SDE overlap length, and sheet resistance were controlled by the energy of preamorphization implantation, and the first two of these parameters were independent of dopant dosage. This allowed us to design strongly activated and abrupt box-like dopant profiles. With this technique, we obtain improvements in drive current of 13 and 8%, respectively, for p- and n-metal oxide semiconductor field effect transistors at and without inducing any short-channel deterioration. © 2004 The Electrochemical Society. All rights reserved.

Size difference in dielectric-breakdown-induced epitaxy in narrow n- and p-metal oxide semiconductor field effect transistors

The physical dimension of the hillocks formed during gate-dielectric-breakdown-induced epitaxy (DBIE) is found to be dependent on transistor type. When narrow transistors of area between 3.0×10−10 and 8.0×10−10 cm2 with a gate oxide ranging from 16 to 33 Å electrically stressed in inversion mode under the same accelerated stress condition, the DBIEs formed in the n-metal oxide semiconductor field effect transistor (MOSFET) are found to be always about 2 times or more larger than that in the p-MOSFET. The difference in the DBIE dimensions is primarily attributed to a larger percolation leakage current in the n-MOSFET during the gate oxide breakdown transient.

Nanoscale silicon MOSFETs: A theoretical study

We have carried out extensive numerical modeling of double-gate, nanoscale silicon n-metal oxide semiconductor field effect transistors (MOSFETs) with ultrathin, intrinsic channels connecting bulk, highly doped electrodes. Our model takes into account two most important factors limiting the device performance as the gate length is reduced, namely the gate field screening by source and drain, and quantum mechanical tunneling from source to drain. The results show that the devices with small but plausible values of gate oxide thickness t/sub ox/ and channel thickness t (both of the order of 2 nm) may retain high ON current, good saturation and acceptable subthreshold slope even if the gate length L is as small as /spl sim/5 nm, with voltage gain above unity all the way down to L/spl ap/2 nm (channel length L/sub c/=L+2t/sub ox//spl ap/5 nm). However, as soon as L is decreased below /spl sim/10 nm, specific power (per unit channel width) starts to grow rapidly. Even more importantly, threshold voltage becomes an extremely sensitive function of L,t, and t/sub ox/, creating serious problems for reproducible device fabrication.

Off-axis Electron Holography for 2D Dopant Profiling in p- and n-Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)

Off-axis Electron Holography for 2D Dopant Profiling in p- and n-Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)

Method to characterize the three-dimensional distribution of focused ion beam induced damage in silicon after 50 keV Ga+ irradiation

In this article we report the straggling of long-range implantation damage in silicon in the forefront of a focused ion beam induced amorphization zone. Irradiation was carried out at room temperature at a current density of 0.75 A cm−2 (5×1018 ions/cm2 s) using 50 keV Ga+ ions. A highly sensitive tool for detection, an n-metal–oxide–semiconductor field effect transistor is used to quantify and to characterize the distribution profile of ion beam induced electroactive defects. Scanning the beam over active devices allows the extraction of a three-dimensional profile of defects. In situ monitoring of the drive current and intermitting charge pumping measurements revealed the progressive nature of the damage, the generation of interface states, and the lateral extension of irradiation related defects. Far reaching damage cascades extend at least 300 nm in the beam direction and about 220 nm perpendicular to the beam direction of the substrate and define the region of electrically active defects due to particle beam exposure. The long range of the implantation damage is confirmed by binary collision simulations that take the crystallinity of the target into account.

Impact of Indium and Boron Interaction on Device Performance for Short and Narrow Channel n-Metal Oxide Semiconductor Field Effect Transistors

The effects of indium and boron interaction in the channel region on device performance have been investigated. The two main areas of focus are the impact of replacing boron with indium as the channel and pocket implants. These are assessed based on the experimental results of short channel effects (SCE) and reverse short channel effects (RSCE). SCE and RSCE are significantly improved by integrating high-dose boron pocket and low indium implant energy, respectively. Experiments done using an indium pocket show severe degradation in SCE control, possibly due to poor activation of the indium dopant. Last, significant improvement in reverse narrow channel effects has been demonstrated by indium channel narrow devices. All experimental data are supported with process and device simulation results using TSUPREM4 and MEDICI, respectively. This allows a correlation between the channel-doping profile and the electrical data. © 2002 The Electrochemical Society. All rights reserved.

Extraction of oxide trap properties using temperature dependence of random telegraph signals in submicron metal–oxide–semiconductor field-effect transistors

Random telegraph signals (RTS) in the drain voltage of light-doped drain n-metal–oxide–semiconductor field effect transistors with W×L=0.5×0.35 μm2 were investigated in the 300–230 K temperature range. The mean capture and emission times were studied as a function of gate voltage as well as temperature in the RTS. A method was developed where several trap characteristics can be extracted, including the position, barrier energy for capture, enthalpy, and entropy associated with emission of an electron, as well as screened scattering coefficient for carrier mobility as a function of temperature. This article reports on a single trap as an example. The position of the trap in the oxide (Tox=70 Å) was found to be 12 Å and, as expected, independent of temperature. The mean capture and emission times exhibited an increase as the temperature is decreased, following a thermally activated process. Utilizing these observations and the temperature dependence of the drain current, the gate voltage dependence of the trap binding energy, and capture activation energy was evaluated. The capture cross-section prefactor (σ0) was calculated using temperature dependence of capture and emission times. These two independent calculations showed almost two orders of magnitude difference in σ0, which is unrealistic. In order to remedy this, the trap binding energy was resolved into entropy and enthalpy components, which were evaluated as a function of gate voltage using the RTS data. The relative contributions of charge carrier mobility and number fluctuations on RTS amplitude were studied as a function of temperature. The mobility fluctuations were found to dominate over number fluctuations over the whole temperature range, and this dominance was found to be more pronounced at higher temperatures. The scattering coefficient due to screened Coulomb scattering effect was computed from the measured RTS data as a function of channel carrier density.

Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric

We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si/sub 3/N/sub 4/) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO/sub 2/) are observed.

Impact of the Stress on the Sub-Micron N-Metal Oxide Semiconductor Field Effect Transistor Characteristics

In this paper, we present a drain current model for stressed short-channel MOSFET's. Stress conditions are chosen so that the interface states generated by hot-carriers are dominant. The defects generated during stress time are simulated by a spatio-temporal gaussian distribution. The parasitic source and drain resistances are included. We also investigate the impact of the interface charge density, generated during stress, on the transconductance. Simulation results show a significant degradation of the drain current versus stress time.

Kink-Related Excess Noise in Deep Submicron Partially and Moderately Fully Depleted Unibond N-Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

In this paper, the low-frequency excess noise due to the kink effect in deep submicron unibond N-metal oxide semiconductor field effect transistor (N-MOSFETs) is investigated. Drain current power spectral density measurements are performed for partially and moderately fully depleted and body-tied devices. The behavior of this effect with the frequency is thoroughly analysed and the control of such a noise overshoot by applying a back-gate voltage is also demonstrated and discussed. A comparison between unibond and SIMOX technologies, in terms of noise behavior, is presented. Finally, the impact of the body contact on the noise is also shown.