N-metal Oxide Semiconductor Field-effect Transistors Research Articles

The defects of reported TID reinforced structures and the improved structure

We find that the previously reported P-edge N-Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET) and dummy gate-assisted (DGA) NMOSFET, to resist the total ionizing dose (TID) effect, have a fatal drawback in that they can only work under a very low drain voltage (Vdd). This paper proposes and demonstrates an improved structure, called P+ edge source NMOS (PES-NMOS), in which the heavily P+ doped belts are only formed on both sides of the source region close to the shallow trench isolation (STI). Both the TCAD software simulations and radiation experiments show that the turn-off current (Ioff) of the PES-NMOS device under 1.8 V Vdd is about 4 to 5 orders of magnitude smaller than that of the control group without reinforcement structure at 300 krad(Si) TID. This result proves that the PES-NMOS can well resist the TID effect and solve the fatal drawback of the reported structures. With the continuous progress of the CMOS process, the thickness of gate oxide becomes very thin, while STI is relatively thick, so the total dose effect on STI is still significant. Therefore, the importance of using the PES-NMOS to suppress the parasitic channel of STI and overcome the shortcomings of the ELT is increasing. Index termsP+ edge source NMOS, total ionizing dose(TID) effect, radiation experiments, radiation hardening by design(RHBD).

Transient characteristics simulation of total ionizing dose effect on Si n-metal-oxide-semiconductor field effect transistor under different gate voltage

In this work, we establish a novel numerical model of total ionizing dose effect and use it to simulate the radiation degradation of Si n-metal-oxide-semiconductor field effect transistor (NMOSFET) under different bias voltages. The model is based on the capture/emission process of traps, and is used to simulate the transient characteristics of semiconductor devices under total ionizing dose effect. In the simulation, the changes of trapped holes in Si/SiO<sub>2</sub> interface and gate oxide layer are extracted, and it is found that the number of trapped holes at different positions tends to be saturated with the increase of the total dose. When the radiation bias voltage is positive, the degradation amplitude of the threshold voltage is significantly higher than that when the radiation bias voltage is negative. Whether the gate is applied with positive bias or negative bias during the radiation, the degradation amplitude of the threshold voltage shows a trend of first increasing and then decreasing with the increase of the absolute value of radiation bias voltage. Radiation bias voltage also has a certain effect on the annealing effect after radiation. If a gate bias voltage is applied to the device during the annealing, the electrical characteristics recovery amplitude of the device is lower than that under zero bias voltage.

Work Function Extraction of Transparent Conducting Indium Oxide Films Used As Gate Electrode for MOSFET

Indium Oxide (In2O3) has received a great deal of attention recently as a transparent conducting oxide (TCO) semiconductor that finds applications in photovoltaic solar cells, transparent windows [1] and flat panel displays due to its high electrical conductivity and good optical transparency in the visible region [2]. It is critical to understand the work function (WF) of a material since it is an important characteristic which has an impact on the device performance.In this work, WF of In2O3 has been estimated by fabricating n-Metal Oxide Semiconductor Field Effect Transistor (NMOSFET). Fabrication of two MOSFET devices has been carried out using four-level mask. The source and drain contacts for both the devices have been prepared by using Aluminum metal. The gate contact for one of the MOSFET devices was prepared using Aluminum metal and transparent conducting In2O3 is used as the gate contact for the second MOSFET. Aluminum deposition was carried out using thermal evaporation technique. A 2-inch copper-backed indium target is used to deposit thin films of In2O3 by RF magnetron sputtering and varying the oxygen gas flow. The substrate temperature is held constant at room temperature. Electrical characterization is performed on the fabricated MOSFETs which is further used in extracting the WF of In2O3 thin films. Timo Jäger, Yaroslav E. Romanyuk, Shiro Nishiwaki, Benjamin Bissig, Fabian Pianezzi, Peter Fuchs, Christina Gretener, Max Döbeli, and Ayodhya N. Tiwari , "Hydrogenated indium oxide window layers for high-efficiency Cu(In,Ga)Se2 solar cells" , Journal of Applied Physics 117, 205301 (2015)Min-Suk Lee, Won Chel Choi, Eun Kyu Kim, Chun Keun Kim, Suk-Ki Min, Characterization of the oxidized indium thin films with thermal oxidation, Thin Solid Films, Volume 279, Issues 1–2, 1996, Pages 1-3, ISSN 0040-6090.

Carbon Incorporation into Substitutional Silicon Site by Molecular Carbon Ion Implantation and Recrystallization Annealing as Stress Technique in n-Metal–Oxide–Semiconductor Field-Effect Transistor

Since the lattice constant of silicon-carbon (Si:C) is smaller than that of Si, Si:C embedded in the source and drain (e-Si:C S/D) can induce tensile stress in the channel and improve the electron mobility of n-metal–oxide–semiconductor field-effect transistor (nMOSFETs). In this research, molecular carbon (C) ion implantation and recrystallization schemes employed to achieve strained Si:C films with a high substitutionally incorporated carbon concentration ([C]sub) and a high ratio of substitution were studied. Several recrystallization techniques including rapid-thermal-annealing (RTA)-based solid phase epitaxy (SPE), spike annealing, and nonmelt laser annealing have been used to optimize C incorporation into Si and strain application. Results of these different implantation and annealing techniques are compared and discussed. Furthermore, we proposed the first recrystallization by nonmelt laser annealing and the co-incorporation of a dopant that increases the rate of Si regrowth and has a covalent radius slightly different from that of Si. These processes markedly promoted the recrystallization of C densely incorporated in an amorphous Si layer and improved the crystallinity of strained Si:C films while maintaining a high [C]sub at a high ratio of substitution.

Optimal Channel Ion Implantation for High Memory Margin of Capacitor-Less Memory Cell Fabricated on Fully Depleted Silicon-on-Insulator

The effect of channel doping concentration on the memory margin of capacitor-less (Cap-less) memory cells fabricated on fully depleted silicon-on-insulator (SOI) n-metal–oxide–semiconductor field-effect transistors (MOSFETs) was investigated. It was observed that the memory margin of Cap-less memory cells is significantly varied by the channel doping concentration, i.e., it increases with doping concentrations up to 1.4 ×1017 cm-3 and then decreases with higher doping concentrations. In particular, at a concentration of 1.4 ×1017 cm-3 it increased 1.8 times compared with that at 1.5 ×1015 cm-3. This gives rise to speculation that the memory margin of Cap-less memory cells fabricated on fully depleted SOI n-MOSFETs can be increased by enlarging the lateral electric field and can be decreased by reducing the current density. These results suggest that a higher memory margin in Cap-less memory cells can be obtained by optimizing channel doping concentration in fully depleted SOI n-MOSFETs.

Comparative study of self-heating effect on electron mobility in nano-scale strained silicon-on-insulator and strained silicon grown on relaxed SiGe-on-insulator n-metal–oxide–semiconductor field-effect transistors

From the viewpoint of the silicon thickness limit for mobility enhancement in a strained Si channel, we investigated the difference in the self-heating effect on electron mobility between strained silicon-on-insulator (sSOI) and strained Si grown on relaxed SiGe-on-insulator (ε-Si SGOI) n-metal–oxide–semiconductor field-effect transistors (MOSFETs) as a function of silicon thickness. We found, for the first time, by numerical simulation that when considered with the presence of self-heating in the silicon thickness range from 5 to 10 nm, the reduction in the mobility enhancement ratio of sSOI n-MOSFETs is less than that of ε-Si SGOI n-MOSFETs by numerical simulation. In addition, we confirmed that the quantum size effect, occurring at the peak mobility value of a 3 nm silicon thickness, disappeared in sSOI n-MOSFETs but was suppressed in ε-Si SGOI n-MOSFETs. Therefore, we propose that an sSOI n-MOSFET is a more promising device than a ε-Si SGOI n-MOSFET for high-performance devices with a design rule of less than 45 nm.

Traps identification in silicon nanocrystals memories by low noise technique

This work reports the extraction of oxide traps properties of n-metal–oxide–semiconductor field-effect transistors with W × L = 0.5 × 0.1 μm 2 using random telegraph signals (RTS) techniques. RTS study of nc-Si has been performed on thin tunnel oxides from 0.8 to 2.0 nm. RTS signals were two or more levels switching events observed on the drain current of transistors with and without nc-Si. The simple two levels RTS 1 noise was observed on samples without nc-Si. On transistors with nc-Si we distinguish two different RTSs (RTS 2 and RTS 3). RTS signal variations with temperature have shown that there's three slow interfacial traps located at E c — 0.26 eV (trap1), E c — 0.23 eV (trap2) and E c — 0.2 eV (trap3). The spatial localization of traps 1, 2 and 3 from the Si–SiO 2 interface are determined using numerical simulations ( x Trap1 ≈ 0.6 nm, x Trap2 ≈ 0.8 nm and x Trap3 ≈ 0.4 nm). RTS noise observed on these devices is attributed to traps localized precisely at the interface thermal oxide/deposited control oxide. (RTS 1) noise is attributed to trap1 and (RTS 2, RTS 3) to traps 2 and 3. From RTS analysis in frequency domain, we extract the power spectrum density of the drain current noise (PSD). From these PSDs we have measured the cut-off frequencies of a single trap even at very low frequencies (for RTS 1 noise f c = 5 Hz (trap1) and for RTS 2 noise f c1 = 2 Hz (trap2), f c2 = 130 Hz (trap3)). These results are in good agreement with those obtained by analysis in time domain and confirm the localization of each trap from the Si–SiO 2 interface.

Dependence of Electrical Characteristics on Si Thickness and Ge Concentration for Unstrained Si Grown on Strained SiGe-on-Insulator n-Metal–Oxide–Semiconductor Field-Effect Transistor

The dependencies of the electrical characteristics of n-metal–oxide–semiconductor field-effect transistors (n-MOSFETs) on the nano-scale Si thickness (<20 nm) and Ge concentration for unstrained Si grown on strained SiGe-on-insulator were investigated. As the Si thickness decreased, the electron mobility decreased more significantly than the strained Si n-MOSFET grown on relaxed SiGe-on-insulator (SGOI). In addition, the electron mobility decreased with increasing the Ge concentration, contrary to strained Si SGOI n-MOSFET.

Effects of nitrogen-incorporated interface layer on the transient characteristics of hafnium oxide n-metal–oxide–semiconductor field-effect transistors

In this letter, we present the effects of the nitrogen-incorporated interface on threshold voltage shift (ΔVth), which was induced by charge trapping and detrapping in hafnium oxide (HfO2) n-metal–oxide–semiconductor field-effect transistors. Under the various gate voltage conditions, the nitrogen-incorporated interface showed a smaller ratio of interface charge density to total charge density (Nit∕Ntotal) due to its thinner interface thickness and lower energy band offset. In addition, the degradations of the interface quality and the mobility under the stress condition were less severe for the nitrogen-incorporated interface devices.

Method to characterize the three-dimensional distribution of focused ion beam induced damage in silicon after 50 keV Ga+ irradiation

In this article we report the straggling of long-range implantation damage in silicon in the forefront of a focused ion beam induced amorphization zone. Irradiation was carried out at room temperature at a current density of 0.75 A cm−2 (5×1018 ions/cm2 s) using 50 keV Ga+ ions. A highly sensitive tool for detection, an n-metal–oxide–semiconductor field effect transistor is used to quantify and to characterize the distribution profile of ion beam induced electroactive defects. Scanning the beam over active devices allows the extraction of a three-dimensional profile of defects. In situ monitoring of the drive current and intermitting charge pumping measurements revealed the progressive nature of the damage, the generation of interface states, and the lateral extension of irradiation related defects. Far reaching damage cascades extend at least 300 nm in the beam direction and about 220 nm perpendicular to the beam direction of the substrate and define the region of electrically active defects due to particle beam exposure. The long range of the implantation damage is confirmed by binary collision simulations that take the crystallinity of the target into account.

Extraction of oxide trap properties using temperature dependence of random telegraph signals in submicron metal–oxide–semiconductor field-effect transistors

Random telegraph signals (RTS) in the drain voltage of light-doped drain n-metal–oxide–semiconductor field effect transistors with W×L=0.5×0.35 μm2 were investigated in the 300–230 K temperature range. The mean capture and emission times were studied as a function of gate voltage as well as temperature in the RTS. A method was developed where several trap characteristics can be extracted, including the position, barrier energy for capture, enthalpy, and entropy associated with emission of an electron, as well as screened scattering coefficient for carrier mobility as a function of temperature. This article reports on a single trap as an example. The position of the trap in the oxide (Tox=70 Å) was found to be 12 Å and, as expected, independent of temperature. The mean capture and emission times exhibited an increase as the temperature is decreased, following a thermally activated process. Utilizing these observations and the temperature dependence of the drain current, the gate voltage dependence of the trap binding energy, and capture activation energy was evaluated. The capture cross-section prefactor (σ0) was calculated using temperature dependence of capture and emission times. These two independent calculations showed almost two orders of magnitude difference in σ0, which is unrealistic. In order to remedy this, the trap binding energy was resolved into entropy and enthalpy components, which were evaluated as a function of gate voltage using the RTS data. The relative contributions of charge carrier mobility and number fluctuations on RTS amplitude were studied as a function of temperature. The mobility fluctuations were found to dominate over number fluctuations over the whole temperature range, and this dominance was found to be more pronounced at higher temperatures. The scattering coefficient due to screened Coulomb scattering effect was computed from the measured RTS data as a function of channel carrier density.

Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric

We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si/sub 3/N/sub 4/) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO/sub 2/) are observed.

Observation and modeling of random telegraph signals in the gate and drain currents of tunneling metal–oxide–semiconductor field-effect transistors

Parallel measurements of random telegraph signals (RTS) in the gate and drain currents of n-metal–oxide–semiconductor field-effect transistors with 1.3-nm-thin gate oxides are presented. RTS appear simultaneously in both currents. Contrary to what could be expected, the signals have opposite signs in the gate and drain currents. A model is proposed to explain this phenomenon by the Schottky effect. The relative amplitude of the signal fluctuation in the gate current is significantly higher than that in the drain current. Therefore, the gate current is a much more sensitive indicator for RTS than the drain current.

Evidence for an additional noise source modifying conventional 1/f frequency dependence in sub-μm metal–oxide–semiconductor field-effect transistors

Flicker noise measurements for n-metal–oxide–semiconductor field-effect transistors have been carried out under a wide range of bias conditions. The experiments show excess noise over an ideal 1/f noise spectrum at around 1–10 kHz frequency range, which is independent of the drain voltage. The origin of the additional noise is the Shockley–Read–Hall generation–recombination process occurring near the drain in the channel. Monte Carlo device simulations confirmed the excess noise origin as well as the observed reduction of its magnitude with increasing gate voltage.

Random telegraph signals and low-frequency noise in n-metal–oxide–semiconductor field-effect transistors with ultranarrow channels

The characteristics of low-frequency noise in n-metal–oxide–semiconductor field-effect transistors with ultranarrow channels have been investigated through random telegraph signals and low-frequency noise spectroscopy. Random telegraph signals with very large amplitude (∼70%) are observed in weak inversion at room temperature. Low-frequency noise spectra having both 1/fn and Lorentzian type are found separately in the same channel at various gate bias voltages. The observations strongly suggest that the low-frequency noise is dominated by carrier mobility fluctuation in weak inversion and by carrier number fluctuation under high-field conditions in an ultranarrow channel.

Kink-Related Excess Noise in Deep Submicron Partially and Moderately Fully Depleted Unibond N-Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

In this paper, the low-frequency excess noise due to the kink effect in deep submicron unibond N-metal oxide semiconductor field effect transistor (N-MOSFETs) is investigated. Drain current power spectral density measurements are performed for partially and moderately fully depleted and body-tied devices. The behavior of this effect with the frequency is thoroughly analysed and the control of such a noise overshoot by applying a back-gate voltage is also demonstrated and discussed. A comparison between unibond and SIMOX technologies, in terms of noise behavior, is presented. Finally, the impact of the body contact on the noise is also shown.

Effect of the forward biasing the source-substrate junction in n-metal–oxide–semiconductor transistors for possible low power complementary metal–oxide–semiconductor integrated circuits’ applications

The use of forward biasing the source-substrate junction in metal–oxide–semiconductor transistors, to reduce its threshold voltage is a simple method to realize low power complementary metal–oxide–semiconductor integrated circuits. A 2 μm long n-metal–oxide–semiconductor field effect transistor was used as the device under test. The threshold voltage was measured in the temperature range of 300–77 K, using two different methods. The classic long channel threshold voltage model was fitted by optimization to the experimental data of the reverse-biased substrate, and the model with the fitted parameters was used to calculate the threshold voltage under forward-biased substrate conditions. The agreement between the fitted and extrapolated threshold voltage with the experimental values demonstrated the validity of this classic model for a substrate forward bias up to 0.5 V, and for a wide temperature range.

Observation of channel shortening in n-metal–oxide–semiconductor field-effect transistors arising from interconnect plasma processing

Very recently we have demonstrated the possible role of an interconnect layout in the degradation of n-metal–oxide–semiconductor field-effect transistors (MOSFETs) during interconnect plasma processing. It was suggested that this role is that of shaping the potential differences between the n-MOSFET’s terminals in such a way as to electrically stress the device. In this study, we further investigate this degradation and examine its effect on hot carrier reliability. Shifts in gm and Vth after a brief hot carrier stress have shown the weak stress resistance of the n-MOSFETs. After additional charge pumping and transconductance measurements, it is suggested that this weak resistance is due to a channel shortening effect in as-processed devices induced by a positive oxide-trapped charge overlapping the drain edge of the channel. Therefore, even a slight change in the magnitude of the charge by either electron or hole injection at that edge ultimately leads to changing the effective channel length and, hence, most of the dc parameters of the n-MOSFETs.

Identification of isolation-edge related random telegraph signals in submicron silicon metal–oxide–semiconductor field-effect transistors

In this letter, evidence is given for a new class of random telegraph signals (RTSs) in submicron n-metal–oxide–semiconductor field-effect transistors (n-MOSFETs). These two-level fluctuations not only occur when the MOSFET is biased in linear operation but also when it is operated in the source or drain-substrate diode mode. A detailed investigation of the RTS parameters, i.e., the amplitude, the emission, and the capture time constants, reveal a close correlation with the current through the forward biased drain- (or source-) substrate diode. At the same time, from the substrate bias dependence of the trap characteristics, it is inferred that it behaves like a near-interface oxide trap. From this, it is concluded that the most likely position is along the channel width perimeter, at the isolation edges of the transistors and close to the source or drain junction.

Field and temperature effects on oxide charge detrapping in a metal–oxide–semiconductor field effect transistor by measuring a subthreshold current transient

A technique to characterize oxide charge detrapping in a Fowler–Nordheim stressed n-metal–oxide–semiconductor field effect transistor is proposed. This technique consists of two alternating phases, an oxide charge detrapping phase and a subthreshold current measurement phase. An analytical model relating a subthreshold current transient to oxide charge density and detrapping time constants was derived. By varying the gate bias in the detrapping phase and the ambient temperature, the field and temperature dependences of oxide charge detrapping can be obtained from the subthreshold current transients measured.