Observation of channel shortening in n-metal–oxide–semiconductor field-effect transistors arising from interconnect plasma processing

Abstract

Very recently we have demonstrated the possible role of an interconnect layout in the degradation of n-metal–oxide–semiconductor field-effect transistors (MOSFETs) during interconnect plasma processing. It was suggested that this role is that of shaping the potential differences between the n-MOSFET’s terminals in such a way as to electrically stress the device. In this study, we further investigate this degradation and examine its effect on hot carrier reliability. Shifts in gm and Vth after a brief hot carrier stress have shown the weak stress resistance of the n-MOSFETs. After additional charge pumping and transconductance measurements, it is suggested that this weak resistance is due to a channel shortening effect in as-processed devices induced by a positive oxide-trapped charge overlapping the drain edge of the channel. Therefore, even a slight change in the magnitude of the charge by either electron or hole injection at that edge ultimately leads to changing the effective channel length and, hence, most of the dc parameters of the n-MOSFETs.