Multiple-valued Logic Circuits Research Articles

Remora Optimized Dynamic Neural Network to Design Low-Power CNTFET Logic Gate Realization with Multiple-Valued Circuits

The emerging trend of new digital technology leads to the requirement of small, faster, and low-power consumed processors. The advanced 5 G technology forces the usage of enhanced battery life, maximized spectral efficiency, etc., these can be achieved by the inclusion of a Carbon nanotube field-effect transistor (CNTFET). The proposed multiple-valued logic circuits (MVL) are designed using some of the unique features of the CNTFET such as high transconductance, setting of desired threshold voltage, and similar mobility of P and N-type devices. For designing low-power and optimized logic gate realization we have utilized the inherent binary gates along with the CMOS architecture. Further, an artificial intelligence approach known as Dynamic Neural Network (DNN) is adopted for the realization of logic gates in the MVL with the employment of lesser MVL operators. To enhance the parameter utilization of DNN with the help of tuning, we exploited the Remora Optimization algorithm (ROA). The results are obtained by conducting experiments on HFSS software. This approach is designed to reduce the static power dissipation, the number of logic gates, and network propagation delay. Compared to the existing methods, the proposed technique outlined a standard voltage of 32 nm that considers 0.9 V supply voltage. The result of our proposed method can be deviated by only 25% and thus outperforms all the other approaches. The standby power consumption of proposed approach is 2.12 W

A review on multiple-valued logic circuits

Since the traditional binary logic has several disadvantages including inaccuracy, high complexity, and limited applications. Multiple-Valued Logic (MVL), which can store more information in one digit than binary logics, require less number of logic gates and take the third value in practical logic problems, is developed and introduced. More information stored per digit leads to higher computational efficiency. Less logic gates results in more spaces on the circuit board. Considering the third value means higher accuracy. In this research, some examples of different MVL circuit are designed to give a rough picture of current research in this domain. These designs are based on ternary and quaternary logics rather than binary logics. Besides, reliability evaluation through mathematical approach is presented in order to prove that the new design is more preferable. This can be carried out with mathematical analysis such as calculating a matrix that reflects its reliability, and simulating different designs to obtain certain values and comparing them with each other. Despite facing various challenges, including complicated physical implementation and difficulty to modulate the signals. This means that there is still potential of further research in this domain of logic circuits. This result in the conclusion that the MVL logic circuits will replace the conventional binary logic circuits in the future, and probably that decimal logic would be developed and no binary-to-decimal conversion unit will be required.

Ternary encoder and decoder designs in RRAM and CNTFET technologies

A possible way for the very large scale integration (VLSI) industry to keep up with the pace of high density, computational capability, and energy efficiency is to look into some technologies ahead of binary logic. In recent years, multiple-valued logic (MVL) has caught the notable attention of digital system designers. The carbon nanotube field effect transistor (CNTFET) has been exclusively used for the implementation of MVL circuits. Resistive random-access memory (RRAM) offers a very durable option for executing the MVL due to its capability of storing various resistance states in one cell. In this paper, a ternary 9:2 encoder and a ternary 2:9 decoder have been designed and simulated using the proposed RRAM-based ternary logic gates with standard 32nm CNTFETs. In comparison to other ternary circuits in the literature, the proposed CNTFET RRAM-based ternary logic circuits show less power consumption, delay, and power delay product (PDP). The power of the CNTFET RRAM-based proposed ternary inverter (TI), ternary NAND (TNAND), and ternary NOR (TNOR) is 32.78%, 51.48%, and 24.14% less than the lowest power of the other designs under consideration. The PVT variations and reliability of the proposed encoder and decoder circuits have also been studied.

Systematic Transistor Sizing of a CNFET-Based Ternary Inverter for High Performance and Noise Margin Enlargement

Noise and variation are the two major challenges for the reliability of digital circuits, especially multiple-valued logic (MVL) circuits where the entire voltage range is divided into some narrow zones. In spite of few correct examples, many ternary inverters with reduced noise margins have been presented in the literature. The defect is mainly because of their improperly shaped voltage transfer characteristic (VTC). With proper transistor sizing, we can rectify the problem and provide uniformly wide noise margin values while maintaining power-delay product (PDP) low. As far as we know, none of the previous ternary inverters has been given based on a methodical transistor sizing procedure. In this paper, a systematic transistor sizing through physical equations is suggested for an existing standard ternary inverter (STI), whose original sizes for the carbon nanotube FETs (CNFETs) are inappropriate. This paper includes a comprehensive investigation to determine appropriate values for the physical parameters of the CNFET-based STI. Compared with the original design, with a negligible increase in circuit delay and area, simulation results show that the proposed ternary inverter can increase noise margin and static noise margin by up to 47.7% and 83.3%, respectively.

Design and Analysis of High-Performance and Low-Power Quaternary Latch,Quaternary D Flip-Flop and XY Flip-Flop

Multiple-valued logic (MVL) circuits propose a number of possible improvements to current VLSI circuit designs. Forexample, serious difficulties with limitations on the number of connections between an integrated circuit and the outside world(pinout concern) and also the number of links within the circuit encountered in some VLSI circuit synthesis could be greatlyreduced if signals in the circuit could assume four or more states instead of only two. This research work shows a quaternarylogic-based latch, a level-sensitive flop, and an edge-sensitive flop. In most of the cases it is seen that a sequential digital circuitproduces two outputs which are complementary to each other. But in most of the designs, there is no need of having both theoutputs of the flip-flops, so one of the quaternary outputs can be removed from the circuit, resulting in a decrease in area andstatic power. In quaternary circuits, several power sources or a single power supply source are employed. Those that haveseveral sources of supply use less energy. In multiple-valued logic we need the design to have multiple logic levels, like inquaternary logic, GND is used for logic ‘0’, 1/3Vdd is used for logic ‘1’, 2/3Vdd is for logic ‘2’, and Vdd is for logic ‘3’. Themulti-Vdd design method is incompatible with the purpose of reducing the inter-chip and intra-chip connections. In order toresolve this, a capacitive divider network is used while designing. The QFF is demonstrated with the necessary simulationresults using LTSpice tool and the simulations are performed using 32nm technology file. Finally, a quaternary shift register isbuilt to demonstrate the applicability and appropriate operation of the proposed QFF in larger sequential circuits.

Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits

The capability of multiple valued logic (MVL) circuits to achieve higher storage density when compared to that of existing binary circuits is highly impressive. Recently, MVL circuits have attracted significant attention for the design of digital systems. Carbon nanotube field effect transistors (CNTFETs) have shown great promise for design of MVL based circuits, due to the fact that the scalable threshold voltage of CNTFETs can be utilized easily for the multiple voltage designs. In addition, resistive random access memory (RRAM) is also a feasible option for the design of MVL circuits, owing to its multilevel cell capability that enables the storage of multiple resistance states within a single cell. In this manuscript, a design approach for ternary combinational logic circuits while using CNTFETs and RRAM is presented. The designs of ternary half adder, ternary half subtractor, ternary full adder, and ternary full subtractor are evaluated while using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions, including different supply voltages, output load variation, and different operating temperatures. Finally, the proposed designs are compared with the state-of-the-art ternary designs. Based on the obtained simulation results, the proposed designs show a significant reduction in the transistor count, decreased cell area, and lower power consumption. In addition, due to the participation of RRAM, the proposed designs have advantages in terms of non-volatility.

Designing positive, negative and standard gates for ternary logics using quantum dot cellular automata

Quantum dot cellular automata (QCA) is one of the promising alternatives for computer circuit design. In this technology cell size is significantly reduced as well as the power dissipation and the chip area. It is possible to design efficient multiple-valued logic circuits using this technology. Theoretical aspects of ternary QCAs (tQCA) are developed and the feasibility of applying these elements is studied. In this paper, we present Negative AND (N-AND), Negative OR (N-OR), Positive AND (P-AND), and Positive OR (P-OR) structure for tQCA. These gates can be the basis of more complex circuits for ternary computation. A new methodology is presented in order to design any standard ternary logic circuit. To achieve this, we have used the combination of one positive and one negative logic gate.

Design of Ternary Logic and Arithmetic Circuits Using GNRFET

Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits. Compared to the conventional and other emerging device technologies, Graphene Nano Ribbon Field Effect Transistor (GNRFET) appears to be very promising for designing MVL logic gates and arithmetic circuits due to some exceptional electrical properties of the GNRFET, e.g., the ability to control the threshold voltage by changing the width of the GNR. Variation of the threshold voltage is one of the prescribed techniques to achieve multiple voltage levels to implement the MVL circuit. This paper introduces a design approach for ternary logic gates and circuits using MOS-type GNRFET. The designs of basic ternary logic gates like inverters, NAND, NOR, and ternary arithmetic circuits like the ternary decoder, 3:1 multiplexer, and ternary half-adder are demonstrated using GNRFET. A comparative analysis of the GNRFET based ternary logic gates and circuits and those based on the conventional CMOS and CNTFET technologies is performed using delay, total power, and power-delay-product (PDP) as the metrics. The simulation and analysis are performed using the H-SPICE tool with a GNRFET model available on the Nanohub website.

A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells

The huge quantity of nodes and interconnections in modern binary circuits leads to extremely high levels of energy consumption. The interconnection complexity and other issues of binary circuits encourage researchers to consider multiple-valued logic (MVL) alternatives. Features of Carbon Nanotube Field-Effect Transistors (CNTFETs) make this technology a potential candidate to implement MVL circuits. In this article, a new systematic methodology is proposed to design ternary logic block circuits based on CNTFETs. The methodology is applied to the design of two basic logic circuits, a half adder and a 1-digit multiplier, which are evaluated through HSPICE simulations. Simulation results indicate improvements over current equivalents in transistor count and PDP mean with the half adder version of 19.2%, and 74.07% respectively, and with the 1-digit multiplier of 24.67% and 81.12% respectively.

Efficient Passive Shielding of MWCNT Interconnects to Reduce Crosstalk Effects in Multiple-Valued Logic Circuits

In this paper, the effectiveness of passive shielding of multiwalled carbon nanotube (MWCNT) bundle interconnects in reducing the crosstalk effects in carbon nanotube FET based ternary circuits is comprehensively investigated. In addition, based on the tighter sublithographic pitch of MWCNTs compared to Cu, we decrease the space between the carbon nanotube (CNT) interconnects to reduce the area overhead, while still having significantly higher effectiveness compared with Cu. The worst-case crosstalk delay and noise for passively shielded MWCNT and Cu wires at 14 nm technology are evaluated using comprehensive HSPICE simulations. The results indicate that the crosstalk delay and noise area in the efficient passively shielded MWCNT bundle interconnects are much smaller than the shielded Cu wires for ternary logic. Furthermore, the impacts of process variation on the crosstalk effects in these interconnects in ternary logic are investigated using Monte Carlo simulations. The results demonstrate the robustness of the passively shielded MWCNT bundles in ternary logic.

Approach for MVL design based on armchair graphene nanoribbon field effect transistor and arithmetic circuits design

This paper presents the approach for multiple-valued logic (MVL) design and implementing the arithmetic circuit based on armchair graphene nanoribbon field effect transistors (GNRFETs). For this purpose, the values of the threshold voltages are obtained for GNRFETs for utilizing in MVL. The Id-Vgs curve is drawn for all n-type GNRFETs by Synopsys HSPICE tools. Moreover, the width variations and band gap energy are scrutinized. The value of threshold voltage for range of N ​= ​3p+1 is more than N ​= ​3p. These observations exhibit that variation of the threshold voltages can be utilized for a circuit design based on GNRFET. Furthermore, the sub-threshold swing is obtained. As a proof of the concept, the ternary arithmetic circuits based on GNR are designed with 0.5 ​V supply voltage. The computational results confirm the threshold voltages values as well as the suitable figure of merits of using GNRFETs in multiple-valued logic circuit design.

Novel energy-efficient and high-noise margin quaternary circuits in nanoelectronics

Multiple-valued logic (MVL) circuits reduce the complexity of connections, thereby decreasing power consumption and chip area. In the recent years, many studies have been conducted on multiple-valued logic due to the high potentials of carbon nanotube transistors in designing these circuits. (MVL) circuits have less noise margin in comparison to the binary ones because of the adjacency of the levels. In this paper, the quaternary logic gates were designed using a novel structure and two separated paths with diode connection to generate ‘1’ and ‘2’ logic levels. This allowed the better adjustment of parameters, increased noise margin, and reduced the power consumption in the ‘1’ and ‘2’ logic levels. A new method was also developed to design quaternary combinational circuits; this method was implemented in the full adder circuit. The designs were simulated using the HSPICE software and the 32 nm Stanford CNTFET model. The simulation results indicated significant improvements in terms of power consumption, PDP, and noise margins in the new model, as compared to the prior works. The PDP improvements were about 79% and 63% for the proposed buffer and SQI gates, respectively, while it was 70% for the quaternary full adder design, as compared to the best single supply-based work reported so far. Also, noise margins were improved in the proposed buffer, getting close to an ideal noise margin of about Vdd/6.

Analytical Review of Noise Margin in MVL: Clarification of a Deceptive Matter

Multiple-valued logic (MVL) can lead to fewer interconnections inside and outside a chip. It can also increase computational performance. Despite these intrinsic advantages, MVL circuits are more prone to noise than the binary counterparts. Since the voltage range is divided into some narrow zones, it is essential to consider noise margins carefully when designing MVL circuits in order to make certain of their suitability and adequate reliability. Several ternary and quaternary inverters, whose voltage transfer characteristics (VTC) suffer from reduced noise margins, have been presented in the literature. This shows that further clarification is definitely required. In this paper, the correct VTC curve of a ternary inverter with proper attributes is clarified. The explanations go beyond ternary logic to cover quaternary and other MVL systems as well. Then, the paper undertakes a review of noise margin and static noise margin measurements for some well-known ternary and quaternary inverters. Besides, the effects of process variation on noise margin are studied.

An Energy- and Area-Efficient Approximate Ternary Adder Based on CNTFET Switching Logic

Nowadays, portable multimedia devices have been widely used in low-power structures. Additionally, using approximate computing and multiple-valued logic (MVL) can lead to lower power consumption. Carbon nanotube field effect transistor (CNTFET), with a determinable threshold voltage, is an appropriate choice for designing MVL circuits. In this study, a new approximate ternary full adder is presented based on CNTFET switching logic with the aim of reducing area and energy consumption. The results obtained by the Synopsys HSPICE simulator with the Stanford 32 nm CNTFET technology show that the average power consumption, delay, and energy consumption of the proposed designs are significantly lower than the other conventional and state-of-the-art CNTFET-based ternary circuits. In addition, the proposed ternary full adder is applied to reduce the steps of a ternary multiplier structure and some important metrics such as normalized error distance and energy-error trade-off are calculated to evaluate the efficiency of the proposed circuits. The layout of the proposed design is also plotted to estimate area consumption. Moreover, the approximate design is used for image processing applications such as image multiplying and image blending and the results are accordingly compared with the exact outputs. Similarly, the evaluated peak signal-to-noise ratio and mean structural similarity index metric indicate that the proposed approximate full adder has a proper accuracy for image processing applications.

Evaluation of Low Power and High Speed CMOS Current Comparators

Over the past few decades, CMOS current comparators have been used in a wide range of applications, including analogue circuits, MVL (multiple-valued logic) circuits, and various electronic products. A current comparator is generally used in an ADC (analog-to-digital) converter of sensors and similar devices, and several techniques and approaches have been implemented to design the current comparator to improve performance. To this end, this paper presents a bibliographical survey of recently-published research on different current comparator topologies for low-power and high-speed applications. Moreover, several aspects of the CMOS current comparator are discussed regarding the design implementation, parameters, and performance comparison in terms of the power dissipation and operational speed. This review will serve as a comparative study and reference for researchers working on CMOS current comparators in low-power and high-speed applications.

Multiple-valued logic design based on the multiple-peak BiCMOS-NDR circuits

Three different multiple-valued logic (MVL) designs using the multiple-peak negative-differential-resistance (NDR) circuits are investigated. The basic NDR element, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction-bipolar-transistor (HBT) devices, can be implemented by using a standard BiCMOS process. These MVL circuits are designed based on the triggering-pulse control, saw-tooth input signal, and peak-control methods, respectively. However, there are some transient states existing between the multiple stable levels for the first two methods. These states might affect the circuit function in practical application. As a result, our proposed peak-control method for the MVL design can be used to overcome these transient states.

Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach

In this paper energy-efficient multiple valued logic (MVL) circuits based on carbon nanotube field effect transistor (CNTFET) are proposed. These circuits are designed based on the unique properties of CNTFETs, such as having same mobility for electrons and holes and also capability of adopting desirable threshold voltage by adjusting the CNTs diameters. The proposed designs have high driving capability, larger noise margins and higher robustness as compared to the previous CNTFET-based designs. The proposed quaternary circuits are examined using HSPICE simulator with the standard CNTFET technology. Simulation results demonstrate more energy-efficient and robust operation of the proposed designs, as compared to the other state-of-the-art CNTFET-based MVL circuits, recently presented in the literature. According to the simulation results the proposed STNOT, STNAND and STNOR circuits have on average 82%, 76% and 45% lower power-delay product (PDP), respectively as compared to their state-of-the-art counterparts. In addition, the proposed QNOT, QNAND and QNOR circuits have the average PDP improvements of 79%, 42% and 61%, respectively, as compared the other recently presented CNTFET-based quaternary designs.

Ballistic charge carrier transmission through graphene multi-barrier structures in uniform magnetic field

We investigate charge carrier transport in graphene multi-barrier structures placed in a uniform magnetic field. The transmission coefficient is found analytically by generalizing the transfer matrix method for the case of graphene regions subjected to a uniform magnetic field. The transmission coefficient through the structure can be modulated by varying the gate voltages, the magnetic field and/or the width of the gated regions. Such a configuration could be used in multiple-valued logic circuits, since it has several output states with discrete and easily selectable transmission/current values.

A universal method for designing low‐power carbon nanotube FET‐based multiple‐valued logic circuits

This study presents new low-power multiple-valued logic (MVL) circuits for nanoelectronics. These carbon nanotube field effect transistor (FET) (CNTFET)-based MVL circuits are designed based on the unique characteristics of the CNTFET device such as the capability of setting the desired threshold voltages by adopting correct diameters for the nanotubes as well as the same carrier mobility for the P- and N-type devices. These characteristics make CNTFETs very suitable for designing high-performance multiple-Vth circuits. The proposed MVL circuits are designed based on the conventional CMOS architecture and by utilising inherently binary gates. Moreover, each of the proposed CNTFET-based ternary circuits includes all the possible types of ternary logic, that is, negative, positive and standard, in one structure. The method proposed in this study is a universal technique for designing MVL logic circuits with any arbitrary number of logic levels, without static power dissipation. The results of the simulations, conducted using Synopsys HSPICE with 32 nm-CNTFET technology, demonstrate improvements in terms of power consumption, energy efficiency, robustness and specifically static power dissipation with respect to the other state-of-the-art ternary and quaternary circuits.

Characterization of Multiple-Valued Logic for Dealing with Ambiguity

This paper focuses onr-valued functions monotonic in a partial order relation, which can be interpreted as a relation expressing something about ambiguity. First, necessary and sufficient conditions for anr-valued function to be monotonic in the relation are clarified. After that, minimal and maximal information loss functions are defined as a special part ofr-valued functions monotonic in the relation. We describe a practical application of minimal information loss functions that correct input failures in multiple-valued logic circuits.