Abstract
Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits. Compared to the conventional and other emerging device technologies, Graphene Nano Ribbon Field Effect Transistor (GNRFET) appears to be very promising for designing MVL logic gates and arithmetic circuits due to some exceptional electrical properties of the GNRFET, e.g., the ability to control the threshold voltage by changing the width of the GNR. Variation of the threshold voltage is one of the prescribed techniques to achieve multiple voltage levels to implement the MVL circuit. This paper introduces a design approach for ternary logic gates and circuits using MOS-type GNRFET. The designs of basic ternary logic gates like inverters, NAND, NOR, and ternary arithmetic circuits like the ternary decoder, 3:1 multiplexer, and ternary half-adder are demonstrated using GNRFET. A comparative analysis of the GNRFET based ternary logic gates and circuits and those based on the conventional CMOS and CNTFET technologies is performed using delay, total power, and power-delay-product (PDP) as the metrics. The simulation and analysis are performed using the H-SPICE tool with a GNRFET model available on the Nanohub website.
Highlights
Multiple Valued Logic (MVL) and its’ applications have been studied extensively over the last couple of decades due to the ability of the MVL logic devices to provide an exponentially higher information density compared to the binary logic
The ternary logic system appears to be the most feasible MVL system that can be adopted in the near future because of its simplicity and ease in distinguishing different logic levels as in the binary system
Due to short channel effects, scaling limitations, DIBL, energy consumption, and other signal integrity issues, conventional technologies are not appealing for the MVL system
Summary
Multiple Valued Logic (MVL) and its’ applications have been studied extensively over the last couple of decades due to the ability of the MVL logic devices to provide an exponentially higher information density compared to the binary logic. We present a design approach for GNRFET based ternary logic circuits. The charge transport is mainly due to the tunneling phenomenon through the barriers instead of the thermionic conduction as in the MOS-type FETs. the tunneling mechanism can overcome the fundamental thermionic limit of the MOStype FETs (60 mV/decade), the MOS-type GNRFET is preferred here for designing the ternary logic circuits because of lots of advantages like higher Ion-Ioff ratio due to absence of ambipolar transport, higher Ion, higher transconductance, better saturation behavior due to smaller output conductance, higher cutoff frequency, faster-switching speed, etc. As mentioned earlier if the width of the GNR is such that the number of dimer lines (N ) is equal to 3p or 3p + 1, that ribbon shows semiconducting behavior. Upon close observation of the graph, the threshold voltage of the transistor for different values of N can be measured
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