Abstract
The huge quantity of nodes and interconnections in modern binary circuits leads to extremely high levels of energy consumption. The interconnection complexity and other issues of binary circuits encourage researchers to consider multiple-valued logic (MVL) alternatives. Features of Carbon Nanotube Field-Effect Transistors (CNTFETs) make this technology a potential candidate to implement MVL circuits. In this article, a new systematic methodology is proposed to design ternary logic block circuits based on CNTFETs. The methodology is applied to the design of two basic logic circuits, a half adder and a 1-digit multiplier, which are evaluated through HSPICE simulations. Simulation results indicate improvements over current equivalents in transistor count and PDP mean with the half adder version of 19.2%, and 74.07% respectively, and with the 1-digit multiplier of 24.67% and 81.12% respectively.
Highlights
According to Moore’s law, chip transistor counts have approximately doubled every two years over the last decades with technology scalability
Among the existing new techniques, Carbon Nanotube Field-Effect Transistors (CNTFETs) is one of the demonstrated alternatives to Complementary Metal Oxide Semiconductor (CMOS) transistors, which operates satisfactorily [5], [6]. It reduces transistor size and power consumption and increases the performance compared to current equivalents. These advantages are achievable due to its intrinsic attributes including the high mobility of P-CNTFET and N-CNTFET, and low off-current [7]
In this article, based on the potential of CNTFET ternary circuits, we propose a systematic methodology to implement optimized circuits in terms of power consumption, transistor count and delay
Summary
According to Moore’s law, chip transistor counts have approximately doubled every two years over the last decades with technology scalability. 3 eDCNT where, Vπ is a constant parameter which determines the carbon π -π bound energy in tight bonding with a value of 3.033 eV and e is the electron charge [10]; the Vth has an inverse relation with tube diameter and varies with the tube diameter derived from n1 and n2 This feature, together with other advantages of CNTFETs such as fine pitch and excellent device characteristics, makes them promising candidates for replacing silicon CMOS transistors. Further designs of a ternary half adder and a 1-digit multiplier using pass transistors with a lower transistor count, but high power consumption and delay have been proposed by Srinivasu and Sridharan [14]. Transistor count and delay of this half adder are high, while it is optimum in terms of power consumption
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