A Half Adder Design Based on Ternary Multiplexers in Carbon Nano-Tube Field Effect Transistor (CNFET) Technology

Abstract

In this paper a ternary half adder is proposed and designed using carbon nano-tube field effect (CNFET) transistors. This novel design in ternary logic is based on multiplexers and level converters. The performance of the proposed design is examined against different supply voltages and a range of temperatures and fan-outs. Propagation delay time, power consumption, power-delay product (PDP) and transistor count are compared between the proposed ternary half adder and prior works. It is shown that the delay time in the proposed design can be improved by 75% with respect to other works while the PDP can be improved at least by 5%. Moreover, the transistor count in the novel design is less than other works at least by 10%. Therefore, it can be a promising candidate for the design of next generation of adder circuits in digital logic systems and ALU blocks.