Remora Optimized Dynamic Neural Network to Design Low-Power CNTFET Logic Gate Realization with Multiple-Valued Circuits

Abstract

The emerging trend of new digital technology leads to the requirement of small, faster, and low-power consumed processors. The advanced 5 G technology forces the usage of enhanced battery life, maximized spectral efficiency, etc., these can be achieved by the inclusion of a Carbon nanotube field-effect transistor (CNTFET). The proposed multiple-valued logic circuits (MVL) are designed using some of the unique features of the CNTFET such as high transconductance, setting of desired threshold voltage, and similar mobility of P and N-type devices. For designing low-power and optimized logic gate realization we have utilized the inherent binary gates along with the CMOS architecture. Further, an artificial intelligence approach known as Dynamic Neural Network (DNN) is adopted for the realization of logic gates in the MVL with the employment of lesser MVL operators. To enhance the parameter utilization of DNN with the help of tuning, we exploited the Remora Optimization algorithm (ROA). The results are obtained by conducting experiments on HFSS software. This approach is designed to reduce the static power dissipation, the number of logic gates, and network propagation delay. Compared to the existing methods, the proposed technique outlined a standard voltage of 32 nm that considers 0.9 V supply voltage. The result of our proposed method can be deviated by only 25% and thus outperforms all the other approaches. The standby power consumption of proposed approach is 2.12 W