Multiple Bit Upsets Research Articles

BUFIT: FINE-GRAINED DYNAMIC BURST FAULT INJECTION TOOL FOR EMBEDDED field programmable gate array TESTING

Fault injection (FI) is a well-known method to attack embedded systems, particularly advanced FPGAs and microcontrollers physically. The FPGA-based embedded system constitutes SRAM for configuration data storage. Multiple-bit upset is a main threat for FPGAs due to technology scaling and complex application bit files. Space environments additionally incur radiation threats to these devices. This paper proposes burst error modeling and a burst fault injection tool (BUFIT) to address these issues. BUFIT has been proposed with fine-grained and coarse-grained circuits. Built-in instrumented FPGA-based FI is proposed for effectively injecting MBUs in configuration memory with space adaptive rate for accurately estimating soft errors. Evaluation of proposed BUFIT on Kintex-7 target FPGA to various OR 1200-based workloads is given to analyze the speed up of the proposed technique. Results on the OR 1200 processor show that BUFIT is three and two orders of magnitude faster than existing DPR and SCFIT techniques. It uses only 0.4 % CLB overhead and has negligible impact on FFs of target SFPGAs.

Fault tolerant micro-programmed control unit for SEU and MBU mitigation in space based digital systems

The Micro-Programmed Control Unit (MPCU) offers an alternative to conventional hardwired control circuits by employing a control store for transmitting control signals through stored control bits. Traditionally, Hamming codes are used for Single-Event Upset (SEU) protection in memory components. However, these Error Control Codes (ECC) encounter challenges, such as inconsistent code rates and limited adaptability for Multiple Bit Upsets (MBU). To address MBU protection, ECC codes with soft decoding logic are commonly utilized, leading to increased hardware complexity. This paper introduces a lightweight encoding and hard-decoding logic capable of detecting and correcting up to n2∗ upsets, achieving a code rate of ≈ 0.37. Through evaluations against both traditional and recent ECC methods, the proposed approach demonstrates enhanced fault correction capabilities compared to Hamming codes. Furthermore, it maintains a consistent code rate, incurs lower area overhead, and exhibits less hardware complexity than MBU codes by employing hard decoding logic. The suggested methodology effectively mitigates both MBU and SEUs in control stores, providing reduced delay and making it well-suited for ensuring reliability in high-speed memory applications like MPCUs.

A Hybrid Technique Based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM Arrays

A Hybrid Technique Based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM Arrays

Fault Tolerance Method for Memory Based on Inner Product Similarity and Experimental Study on Heavy Ion Irradiation

As the feature sizes of integrated circuits are reduced to the nanometer scale, the total soft error rate (SER) in memory and the proportion of multiple bit upsets (MBUs) are significantly increasing. In order to ensure the information reliability, many error correction codes with strong error correction ability were proposed, such as Reed–Somolon (RS) code and Bose–Chaudhuri–Hocquenghem (BCH) code. However, these error correction codes have limited error correction capability, high algorithm complexity and large data redundancy. In this paper, a novel fault tolerance method for locating and correcting multiple bit errors in memory is proposed based on data similarity. The proposed method uses the inner product as the metric to analyze the similarity of the pre-protected data from the vertical and horizontal dimensions, respectively, and to construct the model of error location and correction. This method performs encoding and decoding in units of blocks and detecting and correcting in units of words, so it can correct any number of bits in a corrupted word with low redundancy overhead. Finally, irradiation tests were conducted on a commercial SRAM, and the feasibility of the proposed method is verified by using heavy ion [Formula: see text]Kr[Formula: see text] as irradiation source.

The Bitmap Decryption Model on Interleaved SRAM Using Multiple-Bit Upset Analysis

Static random access memory (SRAM) with an interleaved bitmap design is of special concern for space applications because the interleaving architecture improves the efficiency of error correction code for single-event upsets (SEUs) in a harsh radiation environment. However, most of the interleaving layout is kept unreleased from the manufacturer, and determining the interleaving parameters of an intact SRAM is a challenge for the radiation hardening system. This work proposed a theoretical decryption model of conventional interleaved bitmaps based on the principle of multiple-bit upset (MBU) correlation analysis. The decryption method was practically implemented with a commercial SRAM, and its unknown interleaving architecture was resolved by the spatial correlation and MBU distance upon SEU fault injection attack with <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">252</sup> Cf source. The disclosed interleaving architecture, the subbyte characteristics, and the bit subblock distribution of the device under test (DUT) are in good agreement with the bitmap obtained with SEU mapping of the microbeam. This work demonstrates the valid and robust SRAM layout decryption model and provides a viable approach for evaluating correction efficiency and component reliability in the radiation hardening system.

The Characterization of Errors in an FPGA-Based RISC-V Processor due to Single Event Transients

The reliability of processors is a crucial aspect of processor design. In this study, we design a fault injection framework based on Single Event Transients (SET) to understand its impact on an FPGA-based processor. The key objective of this paper is to integrate the framework with the processor and to study the probability of Multiple Bit Upsets (MBUs) due to the SET. To demonstrate the framework, we choose PicoRV32: a RISC-V based processor implemented on a Xilinx Artix-7 FPGA. We follow a two-step process: RTL Simulation-based fault injection and FPGA-based fault injection. Firstly, we perform a Monte-Carlo based RTL simulation of the processor with the fault injection controller integrated with the processor. We allow the error to propagate and identify the probability of MBUs. As a next step, we use this information to implement the fault injection controller for the FPGA implementation. We observe that the probability of the MBUs (more than 1 bit-flip) is nearly 15.23% on average and 96.8% of the total faults injected propagated to registers. Flip-Flop (FF) is found to be the most vulnerable component in the FPGA (79.1% of resources are mapped to FFs). We also observe that the impact of a fault can last across several clock cycles and is heavily dependent on the instruction being executed by the processor.

Reliability of Error Correction Codes Against Multiple Events by Accumulation

Modern nanoscale devices with storage capacity typically implement error correction codes (ECCs) in order to cope with the effects of natural radiation. Thus, different state-of-the-art ECC techniques aim at preventing data corruption when different numbers of errors (or bitflips) occur in the same logical memory word. However, even though bit interleaving prevents a single particle (such as a proton or a neutron) from flipping several cells in the same word, it cannot be discarded that two independent events may affect nearby cells in the same word and, therefore, would provoke a multiple bit upset (MBU) or equivalent. This article studies the reliability of various state-of-the-art ECC techniques designed for memories to maintain their data integrity under radiation or any other hazardous conditions, where said event accumulation is likely to occur. For this purpose, a set of easy-to-use equations will be provided to estimate the probability of error occurrence in a memory that implements different ECCs, as a function of the number of accumulated bitflips, size of the memory, and word size.

重离子在14-nm FinFET SRAM器件引起的单粒子翻转

The characteristic of single-event upset(SEU) in a 14-nm bulk fin field-effect transistor (FinFET) static random access memory(SRAM) is investigated by heavy-ion experiments. The linear energy transfer(LET) threshold 0.1 MeV/(mg/cm2) is obtained by fitting the SEU cross-section using the Weibull function. The contribution of multiple-bit upset(MBU) is investigated. The results show that when the LET is equal to 40.3 MeV/(mg/cm2), greater than 95% of SEU comes from the MBU. Additionally, the SEU cross-section of the FinFET SRAM presents anisotropies for incident angles associated with the fin direction. This research has a certain kind of guiding role in designing of radiation-hardened complementary metal-oxide semiconductor(CMOS) integrated circuits(ICs) based on FinFET technology.

Extensive fault emulation on RFID tags for fault tolerance and security evaluation

Radio frequency identification (RFID) is widespread and still necessary in many important applications. However, and in various significant cases, the use of this technology faces multiple security issues that must be addressed. This is mainly related to the use of RFID tags (transponders) which are electronic components communicating wirelessly, and hence they are vulnerable to multiple attacks through several means. Thus, it is challenging to evaluate the hardness of such devices. To tackle this problem, an extensive fault analysis is performed on an ultra-high frequency (UHF) tag architecture. Tens of millions of single-bit upsets (SBUs) and multiple-bit upsets (MBUs) faults have been emulated randomly on this tag architecture using an FPGA (field programmable gate arrays)-based emulation platform. The emulated faults have been classified into five groups according to faults effect on the tag behavior. Then, we propose a classification of emulated fault in function of MBU size and an error analysis with the aim of distinguishing between major and minor errors. Thus, experimentation results allowed a thorough evaluation of the tag robustness against MBUs. The proposed approach stands for an efficient means for studying tag architectures at the design level and evaluating their robustness and vulnerability to fault attacks and disturbances of harsh environments.

Impact of TMR design layouts on single event tolerance in SRAM-based FPGAs

For highly reliable applications in mission critical systems, the Triple Modular Redundancy (TMR) technique is believed to be a common and effective approach to mitigate Single Event Upsets (SEUs) in Field Programmable Gate Arrays (FPGAs). In one of our neutron test campaigns, we observed an increase of 53.8% in single event tolerance of our optimized Fast Fourier Transform (FFT) design compared with the baseline (i.e., the traditional FFT design), while the increase of the TMR'd optimized FFT design is only 30.8% compared with the baseline. Although it is believed that Multiple-Cell Upsets (MCUs) poses a negative impact on the single event performance of TMR, the results of the TMR'd optimized FFT design are far from our expectations. A large number of preliminary simulations confirm that layout changes have a significant impact on the Multiple-Bit Upsets (MBUs) sensitivity of TMR'd design. This is because in the layout obtained through automatic placement and routing, these replicated modules of the TMR are interlaced with each other. Therefore, MBUs are more likely to induce domain-crossing events and affect two or more TMR modules. To further harden the TMR'd design, either putting three identical circuits of the TMR'd design into three independent blocks or using Dynamic Partial Reconfiguration (DPR) is demonstrated effective in mitigating MBUs in Static Random-Access Memory (SRAM)-based FPGAs.

Comparative Study on the “Soft Errors” Induced by Single-Event Effect and Space Electrostatic Discharge

Single event effect (SEE) and space electrostatic discharge (SESD) are two important types of effects causing spacecraft anomalies. However, it is difficult to differentiate them to identify the root cause of on-orbit anomalies. This paper pioneers the comparative study of the “soft errors” induced by the SEE and SESD with a well-known static random-access memory (SRAM). The similarity and difference of the physical mechanisms between the “soft errors” induced by SEE and SESD are studied with the technology computer-aided design (TCAD) simulations. Meanwhile, the characteristics of the “soft errors” and the relation with external stimulus between SEE and SESD are further investigated with the pulsed laser SEE facility and SESD test system. The results showed that the similar appearances of “soft errors” can be generated by both SEE and SESD, while multiple-bit upset (MBU) has been observed only in SESD testing. In addition, in comparison to the random distribution of SEE sensitivity areas, the SESD sensitivity areas are in closer proximity to the power supply regions. The different symptoms in upsets can be used to identify the root causes of the spacecraft anomalies.

Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial.

Communication systems that work in jeopardized environments such as space are affected by soft errors that can cause malfunctions in the behavior of the circuits such as, for example, single event upsets (SEUs) or multiple bit upsets (MBUs). In order to avoid this erroneous functioning, this kind of systems are usually protected using redundant logic such as triple modular redundancy (TMR) or error correction codes (ECCs). After the implementation of the protected modules, the communication modules must be tested to assess the achieved reliability. These tests could be driven into accelerator facilities through ionization processes or they can be performed using fault injection tools based on software simulation such as the SEUs simulation tool (SST), or based on field-programmable gate array (FPGA) emulation like the one described in this work. In this paper, a tutorial for the setup of a fault injection emulation platform based on the Xilinx soft error mitigation (SEM) intellectual property (IP) controller is depicted step by step, showing a complete cycle. To illustrate this procedure, an online repository with a complete project and a step-by-step guide is provided, using as device under test a classical communication component such as a finite impulse response (FIR) filter. Finally, the integration of the automatic configuration memory error-injection (ACME) tool to speed up the fault injection process is explained in detail at the end of the paper.

Neutron-induced single event upset simulation in Geant4 for three-dimensional die-stacked SRAM* *Project supported by the National Natural Science Foundation of China (Grant Nos. 12035019, 111690041, and 11675233) and the Project of Science and Technology on Analog Integrated Circuit Laboratory, China ((Grant No. 6142802WD201801).

Three-dimensional integrated circuits (3D ICs) have entered into the mainstream due to their high performance, high integration, and low power consumption. When used in atmospheric environments, 3D ICs are irradiated inevitably by neutrons. In this paper, a 3D die-stacked SRAM device is constructed based on a real planar SRAM device. Then, the single event upsets (SEUs) caused by neutrons with different energies are studied by the Monte Carlo method. The SEU cross-sections for each die and for the whole three-layer die-stacked SRAM device is obtained for neutrons with energy ranging from 1 MeV to 1000 MeV. The results indicate that the variation trend of the SEU cross-section for every single die and for the entire die-stacked device is consistent, but the specific values are different. The SEU cross-section is shown to be dependent on the threshold of linear energy transfer (LETth) and thickness of the sensitive volume (Tsv). The secondary particle distribution and energy deposition are analyzed, and the internal mechanism that is responsible for this difference is illustrated. Besides, the ratio and patterns of multiple bit upset (MBU) caused by neutrons with different energies are also presented. This work is helpful for the aerospace IC designers to understand the SEU mechanism of 3D ICs caused by neutrons irradiation.

A Memory Reliability Enhancement Technique for Multi Bit Upsets

Technological advances allow the production of increasingly complex electronic systems. Nevertheless, technology and voltage scaling increased dramatically the susceptibility of new devices not only to Single Bit Upsets (SBU), but also to Multiple Bit Upsets (MBU). In safety critical applications, it is mandatory to provide fault-tolerant systems, providing high reliability while meeting applications requirements. The problem of reliability is particularly expressed within the memory which represents more than 80 % of systems on chips. To tackle this problem we propose a new memory reliability techniques referred to as DPSR: Double Parity Single Redundancy. DPSR is designed to enhance computing systems resilience to SBU and MBU. Based on a thorough fault injection experiments, DPSR shows promising results; It detects and corrects more than 99.6 % of encountered MBU and has an average time overhead of less than 3 %.

FPGA Based Low Area Multi-bit Adjacent Error Correcting Codec for SRAM Application

Mostly random and adjacent error correcting codes are used to protect stored data in SRAMs against multiple bit upsets (MBUs). These MBUs caused by radiation are an important issue related to the reliability of static random access memories (SRAMs). As a result, multiple adjacent bits of a memory are distorted and valuable information is lost. To mitigate these problems, multi-bit adjacent error correcting codes are preferable in SRAM. In this paper, single error correction-double error detection-double adjacent error correction (SEC-DED-DAEC) codes are proposed. The performances of the proposed SEC-DED-DAEC codes are observed in terms of area and delay. Theoretical area overhead of proposed codes is at most 49.98% lower compared to the related design. Also the proposed design has around 28.79% lesser critical path delay compared to existing design. The best improvement achieved in terms of number of look-up table (LUT) and delay are 22.69 and 29.98% respectively compared to other existing codes in FPGA platform. The proposed codes can be used in embedded SRAM applications.

Protecting scratchpad memory addresses against soft errors

Scratchpad memories (SPMs) are intensively utilized in modern embedded processors where a demand on improving reliability without compromising performance-predictability and area/power efficiency is on rise. Our observations imply that one target for this reliability improvement is to combat ever increasing threats of multiple bit upsets (MBUs) occurring in the SPM addresses as well as multiple event transients (METs) happening in the SPM address decoders (SADs). This paper proposes two masking techniques that protect SPM addresses in their lifespan across multiple on-chip structures prone to MBU/MET errors. The strategy behind both techniques is to replicate narrow-width SPM addresses at compile time, and to mask errors at the SAD stage. The first technique is triplication of SPM addresses (TSA), and using a triplicated SAD. For the processors having limited memory address widths, the second technique uses the concept of redundant residue number system to provide a residual replication of SPM addresses (RRSA), and a residually replicated SAD. Simulation results showed that interleaving the retained bits between replicas/residues extends error masking coverage of TSA and RRSA from 86% and 78% to 91% and 97% with no performance loss, while imposing only 0.23% and 0.11% power and 0.02% and 0.01% area to the processor.

Impact of Coulomb elastic scattering of protons and iron ions on single-event upsets in a 22 nm SOI SRAM

The contribution of Coulomb elastic scattering of protons and heavy ions to single-event upsets (SEUs) is concerned in nanometric electronic devices. In this work, Monte Carlo Geant4 simulations are used to investigate the impact of Coulomb elastic scattering of protons and iron ions on SEUs in a 22 nm silicon-on-insulator (SOI) static random access memory (SRAM). The SEU cross section and multiple-bit upset (MBU) proportion versus incident energy curves for protons and iron ions have been estimated for the SRAM thanks to numerical Geant4 simulations. The ionization processes of ionizing radiation causing SEUs are sorted into three parts: direct ionization from primary particles, indirect ionization from Coulomb recoil atoms, and indirect ionization from secondary particles produced by nuclear reactions. Their relative contributions to SEUs and MBUs are analyzed. The contribution of Coulomb elastic scattering to SEUs cannot be neglected in the energy range from 2 to 6 MeV and below 40 MeV for protons and iron ions, respectively. In the case of iron ion incidence, it is observed that the total SEU cross section decreases in the energy range from 16 to 40 MeV. It can be attributed to the decrease in the Coulomb elastic scattering cross section of iron ions. The probability distributions of energy deposited in the sensitive volumes (SVs) are calculated for iron ions with different energies. The sources of energy deposited in an SV can be sorted into three cases. The three parts of the probability distribution of deposited energy corresponding to these three cases change with increasing incident energy, which can well explain the observed SEU response.

Angular Sensitivity of Neutron-Induced Single-Event Upsets in 12-nm FinFET SRAMs With Comparison to 20-nm Planar SRAMs

The angular sensitivity of neutron-induced single-event upsets (SEUs) is studied in 12-nm FinFET SRAMs. Irradiation experiments are performed using a terrestrial environment-compatible source with varying incidence angles. The analyses of the occurrence rates of SEUs and multiple-bit upsets (MBUs) demonstrate that although the SEU rate decreases at grazing incidence, the MBU rate increases when the incidence direction is parallel to the word lines (WLs) of the SRAM array, as similarly observed in our previous experiments for 20-nm planar SRAMs. It is found that the angular response of multiple-cell upsets (MCUs) is different between the 12-nm FinFET and 20-nm planar SRAMs. The comparative analysis of the voltage dependence of the MCU ratio reveals that this difference is due to the different contribution of parasitic bipolar effects (PBEs), which are more significant in the 20-nm planar SRAMs. It is also indicated that in the 12-nm FinFET SRAMs, the contribution of PBEs is relatively large when the incidence angle is parallel to the WLs. Through the characterization of the MCU events, the validity of this picture is confirmed based on the voltage dependence of the pattern-wise MCU ratio with the consideration of the impact of PBEs on fail bit patterns.

Proton-induced single-event effects on 28 nm Kintex-7 FPGA

Proton experiments were performed on Kintex-7 XC7K70T field programmable gate array by using a self-developed test system at EN tandem accelerator in Peking University. The single-event upset and multiple-bit upsets induced by low-energy proton were presented, and a cross section peak under the low-energy protons was tested. Also, the experiments under high-energy protons were performed on the proton cyclotron accelerator in the China Institute of Atomic Energy, cross sections of some blocks in FPGA were obtained. Data of low-energy and high-energy experiments showed that the LET threshold of some resources were different. Results suggest that the low-energy proton-induced single event effect must be considered.

Outstanding Conference Paper Award: 2019 IEEE Nuclear and Space Radiation Effects Conference

In this work, experimental results are presented on single-bit-upsets (SBU) and multiple-bit-upsets (MBU) on a 45 nm SOI SRAM. The upset cross-sections were obtained with accelerated testing using both protons and heavy ions. The proton upset cross-sections were obtained using proton energies ranging from 1 to 500 MeV and the heavy ion data were obtained using ions with effective linear energy transfer (LET) values from 0.6 to 100 . Overall, the SBU data on the 45 nm SOI SRAM showed upset cross-sections-per-bit that were very similar to the cross-sections-per-bit on a 65 nm SOI SRAM for both heavy ion and proton testing. This result continues a trend that has been observed with advanced SOI CMOS SRAMs. In contrast to the SBU data, the MBU data on the 45 nm SRAM showed significantly higher upset cross-sections relative to the 65 nm SRAM. The higher MBU cross-sections were also expected based upon the closer spacing of the nodes in adjacent cells. While the overall trends were anticipated, the major focus of the paper was to understand a diverse range of single event effects that were contributing to the measured upsets. As a function of the incident proton energy, both scattering events and direct ionization upsets were observed. The data also highlighted the unique upset results that are produced at a 90 degree tilt angle. The MBU data showed a very large dependence on the data stored in the SRAM. The data dependence was understood based upon the layout of the SRAM cells and the MBU upsets produced by strikes in common diffusion regions. A detailed analysis of the MBU data showed that almost all of the MBU events occurred in adjacent cells along the bit-lines of the array. This result is very important since the MBU events along the same bit-line will be effectively corrected by error-correctingcode (ECC) circuits. Thus, the higher overall MBU cross-sections that were observed with technology scaling are not a critical issue in SOI SRAMs that use ECC circuits. David F. Heidel received his B.S. degree in physics from Miami University in 1974, and his M.S. and Ph.D. degrees in physics from The Ohio State University in 1976 and 1980 respectively. In 1980, he joined IBM’s Research Division, at the Thomas J. Watson Research Center in Yorktown Heights, NY, working on Josephson superconducting technology. Since