The Characterization of Errors in an FPGA-Based RISC-V Processor due to Single Event Transients

Abstract

The reliability of processors is a crucial aspect of processor design. In this study, we design a fault injection framework based on Single Event Transients (SET) to understand its impact on an FPGA-based processor. The key objective of this paper is to integrate the framework with the processor and to study the probability of Multiple Bit Upsets (MBUs) due to the SET. To demonstrate the framework, we choose PicoRV32: a RISC-V based processor implemented on a Xilinx Artix-7 FPGA. We follow a two-step process: RTL Simulation-based fault injection and FPGA-based fault injection. Firstly, we perform a Monte-Carlo based RTL simulation of the processor with the fault injection controller integrated with the processor. We allow the error to propagate and identify the probability of MBUs. As a next step, we use this information to implement the fault injection controller for the FPGA implementation. We observe that the probability of the MBUs (more than 1 bit-flip) is nearly 15.23% on average and 96.8% of the total faults injected propagated to registers. Flip-Flop (FF) is found to be the most vulnerable component in the FPGA (79.1% of resources are mapped to FFs). We also observe that the impact of a fault can last across several clock cycles and is heavily dependent on the instruction being executed by the processor.