FPGA Based Low Area Multi-bit Adjacent Error Correcting Codec for SRAM Application

Abstract

Mostly random and adjacent error correcting codes are used to protect stored data in SRAMs against multiple bit upsets (MBUs). These MBUs caused by radiation are an important issue related to the reliability of static random access memories (SRAMs). As a result, multiple adjacent bits of a memory are distorted and valuable information is lost. To mitigate these problems, multi-bit adjacent error correcting codes are preferable in SRAM. In this paper, single error correction-double error detection-double adjacent error correction (SEC-DED-DAEC) codes are proposed. The performances of the proposed SEC-DED-DAEC codes are observed in terms of area and delay. Theoretical area overhead of proposed codes is at most 49.98% lower compared to the related design. Also the proposed design has around 28.79% lesser critical path delay compared to existing design. The best improvement achieved in terms of number of look-up table (LUT) and delay are 22.69 and 29.98% respectively compared to other existing codes in FPGA platform. The proposed codes can be used in embedded SRAM applications.