FPGA and ASIC Implementation of SEC-DED-DAEC Codes for SRAM Applications

Abstract

Multiple bit upsets (MBUs) admit progressively in memory density with continual expand. The valuable information of memories are demolished due to soft errors. To avoid these errors in MBUs of memory, error correction codes are introduced. Single error correction-double error detection-double adjacent error correction (SEC-DED-DAEC) codes are used to protect SRAM devices from radiation-induced MBUs. These codes are able to correct single and double adjacent errors, and also detect double errors. In this paper, seven different SEC-DED-DAEC codes have been designed and implemented for static random access memories (SRAM) with word width of 16-bit, 32-bit, and 64-bit. All the codec architectures are simulated and synthesized both in FPGA and ASIC platforms. Performances of different SEC-DED-DAEC codecs are observed in terms of area and delay.