Hardened design based on advanced orthogonal Latin code against two adjacent multiple bit upsets (MBUs) in memories

Abstract

Soft errors have been a concern in memory reliability for many years. With device feature size decreasing and memories density increasing, a single event upset (SEU) in memory may generate adjacent bit upsets in a word that may cause data errors. To avoid data errors in memories, Error Correction Codes (ECCs) are used. As multiple bits affected become frequent, the Single Error Correction (SEC) codes that can correct one bit error per word are not effective against adjacent errors and more advanced ECCs are needed. Orthogonal Latin Square (OLS) codes are a type of one-step majority logic decodable (OS-MLD) codes that have been used to protect memories recently. Although OLS codes can effectively mitigate the multiple bit upsets (MBUs), the impact on the overheads increased by the correction capability improvement is not negligible. In this paper, an optimized Orthogonal Latin Square code capable of two adjacent errors correction is proposed by optimizing the structure of OLS codes parity check matrixes using the proposed block cyclic shift algorithm. The simulation results show that the proposed code not only maintains the advantage of OS-MLD codes, but also has lower overheads than the OLS code capable of double errors correction.