Abstract

The Micro-Programmed Control Unit (MPCU) offers an alternative to conventional hardwired control circuits by employing a control store for transmitting control signals through stored control bits. Traditionally, Hamming codes are used for Single-Event Upset (SEU) protection in memory components. However, these Error Control Codes (ECC) encounter challenges, such as inconsistent code rates and limited adaptability for Multiple Bit Upsets (MBU). To address MBU protection, ECC codes with soft decoding logic are commonly utilized, leading to increased hardware complexity. This paper introduces a lightweight encoding and hard-decoding logic capable of detecting and correcting up to n2∗ upsets, achieving a code rate of ≈ 0.37. Through evaluations against both traditional and recent ECC methods, the proposed approach demonstrates enhanced fault correction capabilities compared to Hamming codes. Furthermore, it maintains a consistent code rate, incurs lower area overhead, and exhibits less hardware complexity than MBU codes by employing hard decoding logic. The suggested methodology effectively mitigates both MBU and SEUs in control stores, providing reduced delay and making it well-suited for ensuring reliability in high-speed memory applications like MPCUs.

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