Multi-level Phase Change Memory Research Articles

Minority-carrier transport through an isotype amorphous-crystalline Ge2Sb2Te5 heterojunction under forward bias

To predict possible minority-carrier effects in multi-level phase change memory devices, minority-carrier transport through an isotype amorphous-crystalline Ge2Sb2Te5 heterojunction under forward bias is studied for the first time. Electron thermionic emission, thermal generation, drift, diffusion, radiative recombination, Auger recombination, Schockley–Read–Hall recombination via conduction band tails, valence band tails, acceptor-type mid-gap, donor-type mid-gap and multivalent defect distributions, as well as surface recombination are considered in the construction of the steady-state Continuity Equation relevant to the representative amorphous-crystalline Ge2Sb2Te5 heterojunction, which is then numerically solved at 0.15 V and 0.40 V using solar cell capacitance simulations. Provided that radiative recombination is negligible and defect distributions within the band gap of either layer are energetically localised, the simulated electron concentration, electron current density and electron quasi-Fermi level distributions across the heterojunction reveal that transport through the amorphous layer limits electron flow through the device. At low applied bias, net recombination and diffusion within the quasi-neutral region (QNR) of the amorphous layer dominate, whereas at larger applied bias, drift across the QNR, due to the electric field induced by the significant majority-carrier current density, as well as surface recombination at the amorphous layer contact contribute significantly. Within the crystalline layer, net generation of electrons supplies the amorphous layer at all biases, assuming that the crystalline layer contact does not limit electron transport. Thus, the effect of forward bias on the dominant transport mechanisms through the amorphous-crystalline Ge2Sb2Te5 heterojunction demonstrated herein represents the key contribution of this paper.

Multi-level phase-change behaviors of Ge2Sb2Te5/Sb7Se3 bilayer films and a design rule of multi-level phase-change films

Multi-level phase-change (MLPC) memory can not only further raise the storage density of high-density phase-change memory, but also have significant applications in neuromorphic computing. However, acquisitions of MLPC materials are very challenging. MLPC is only observed in a small number of phase-change materials and can’t be designed determinately because the mechanism of MLPC emergence has been understood incompletely. Here, we investigate phase-change behaviors of six Ge2Sb2Te5(x nm)/Sb7Se3 (60-x nm) bilayer films with x = 5, 10, 15, 20, 35, and 50. Three-level phase-change memory is observed for five bilayer films with x < 50, but not for one with x = 50, revealing the dependence of MLPC memory on the thickness ratio of two constituent layers composing bilayer films. A parallel resistance model is proposed to describe the measured sheet resistance of bilayer films and can be used to explain the thickness-ratio dependence of three-level phase-change memory very well. Subsequently, a design rule for MLPC memory films is given out unambiguously. Based on the parallel resistance model, MLPC memories are simulated for bilayer and trilayer films. Three-level memory indeed appears in bilayer films only when the design rule is met, confirming the validity of our design rule. Four-level memory is predicted in trilayer films as the design rule is obeyed.

Improvement of Multilevel Memory Performance of MnTe Thin Films by Ta Doping.

The pressing need for data storage in the era of big data has driven the development of new storage technologies. As a prominent contender for next-generation memory, phase-change memory can effectively increase storage density through multilevel cell operation and can be applied to neuromorphic and in-memory computing. Herein, the structure and properties of Ta-doped MnTe thin films and their inherent correlations are systematically investigated. Amorphous MnTe thin films sequentially precipitated cubic MnTe2 and hexagonal Te phases with increasing temperature, causing resistance changes. Ta doping inhibited phase segregation in the films and improved their thermal stability in the amorphous state. A phase-change memory cell based on a Ta2.8%-MnTe thin film exhibited three stable resistive states with low resistive drift coefficients. The study findings reveal the possibility of regulating the two-step phase-change process in Ta-MnTe thin films, providing insight into the design of multilevel phase-change memory.

OML-PCM: optical multi-level phase change memory architecture for embedded computing systems

Unlike Dynamic Random Access Memory (DRAM), Phase Change Memory (PCM) offers higher density, longer data retention, and improved scalability because of its non-volatility and low leakage power. However, Electrically-Addressable PCM (EPCM) has a higher dynamic power and long latency than DRAM. To address these issues, scientists have developed Optically-Addressable PCM (OPCM), which uses 5-level cells instead of 2-level cells in EPCM. A silicon photonic link allows optical signals to reach OPCM cells at a high speed. Hence, OPCM can achieve a higher density while maintaining better performance at multi-level cells and consuming less power per access. However, OPCM is not suitable for general use since the photonic links do not provide an electrical interface to the processor. The aim of this paper is to present a hybrid OPCM architecture based on the use of novel multi-bank clusters with distinctive properties. Electrical-Optical-Electrical conversion (EOE) allows OPCM cells to be randomly accessed by using DRAM-like circuitry. The proposed hybrid design with multi-core processing and OPCM achieves a 2.13x speedup over previous approaches while consuming less Central Processing Unit (CPU) power. It is important to note that the proposed design offers 97 units fewer power-consistent bits than EPCM. In addition, the proposed architecture provides comparable performance and power to DDR4, as well as improved bandwidth density, space efficiency, and versatility. The Gem5 simulator was used to evaluate the design. Based on the outcomes of the analysis, the proposed architecture offers 2.08x and 2.14x better evaluations and density performance than EPCM. Furthermore, the execution time has been reduced by 2.13x, the analysis time by 1.23x, and the composition time by 4.60%.

Crystallization behavior of MnTe/GeTe stacked thin films for multi-level phase change memory

With substantial data storage requirements, enhancing the storage density of emerging non-volatile memories is a common challenge for achieving commercial applications. Phase change memory is capable of multi-level data storage in a storage cell, which can be applied in neural-inspired and all-photonic memory computing. In this study, we propose a MnTe/GeTe stacked thin film structure suitable for multi-level phase change memories and systematically study on the correlation between structure and performance. As the temperature rises, the stacked thin film sequentially crystallizes into form MnTe2, GeTe and Te phases, resulting in three changes in resistance. By utilizing different resistance states, the phase change memory cell based on the MnTe (15 nm)/GeTe (35 nm) stacked thin film can achieve multi-level storage with a 50 ns electrical pulse. The results show that the amorphous thermal stability of the stacked thin films is improved and that the minimal thickness variation before and after crystallization enhances its reliability. Therefore, the MnTe/GeTe stacked thin film is a phase change memory material with favorable structural properties and potential for multi-level storage applications.

Hybrid Program Algorithm Enables Significant Reduction in Write Latency and Power Consumption for Multilevel Phase Change Memory

Hybrid Program Algorithm Enables Significant Reduction in Write Latency and Power Consumption for Multilevel Phase Change Memory

Multilevel optoelectronic hybrid memory based on N-doped Ge2Sb2Te5 film with low resistance drift and ultrafast speed

Multilevel phase-change memory is an attractive technology to increase storage capacity and density owing to its high-speed, scalable and non-volatile characteristics. However, the contradiction between thermal stability and operation speed is one of key factors to restrain the development of phase-change memory. Here, N-doped Ge2Sb2Te5-based optoelectronic hybrid memory is proposed to simultaneously implement high thermal stability and ultrafast operation speed. The picosecond laser is adopted to write/erase information based on reversible phase transition characteristics whereas the resistance is detected to perform information readout. Results show that when N content is 27.4 at.%, N-doped Ge2Sb2Te5 film possesses high ten-year data retention temperature of 175 °C and low resistance drift coefficient of 0.00024 at 85 °C, 0.00170 at 120 °C, and 0.00249 at 150 °C, respectively, owing to the formation of Ge–N, Sb–N, and Te–N bonds. The SET/RESET operation speeds of the film reach 520 ps/13 ps. In parallel, the reversible switching cycle of the corresponding device is realized with the resistance ratio of three orders of magnitude. Four-level reversible resistance states induced by various crystallization degrees are also obtained together with low resistance drift coefficients. Therefore, the N-doped Ge2Sb2Te5 thin film is a promising phase-change material for ultrafast multilevel optoelectronic hybrid storage.

C/Sb2Te3 phase-change heterostructure films with low resistance drift for multilevel phase change memories

Multilevel storage and resistance drift are two challenges in phase-change memories. Here, we report that [C(5 nm)/Sb2Te3(12 nm)]5 phase-change heterostructure film has multilevel phase change properties and low resistance drift. The addition of carbon broke the Sb2Te3 bond and formed new C-Sb and C-Te bonds. The reliability of phase-change heterostructure was demonstrated by transmission electron microscopy. The amorphous resistance drift index of C/Sb2Te3 film was reduced effectively which may be caused by the structure relaxation. In addition, PCM devices based on C/Sb2Te3 phase-change heterostructure films also confirmed the potential of multilevel storage. This research provided a new method to realize multilevel phase-change memories with low resistance drift.

Design space exploration for balanced MLC-PCM programming

Multi-Level Cell Phase Change Memory (MLC PCM) is a non-volatile memory technology that promises high-density data storage. However, MLC PCM suffers from long write latency because changing the state of each memory cell takes a long time and the number of cells that can be written concurrently is limited due to the relatively large size and power consumption of the write drivers. MLC PCM typically divides the write data into multiple cell groups to program cells in batches. The group mapping has a significant impact on the overall latency of write requests. Prior work proposed a group mapping technique for single-level cell (SLC) PCM based on the data pattern of a set of applications. In this work, a larger design space of group mapping is explored for MLC PCM. The specific group mapping for each benchmark is dynamically customized. Our technique leads to a 13.14% reduction in write latency compared to the state-of-the-art method (Du et al., 2013) and shows good temporal consistence in different benchmarks.

HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

We present a 256 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula> 256 in-memory compute (IMC) core designed and fabricated in 14-nm CMOS technology with backend-integrated multi-level phase change memory (PCM). It comprises 256 linearized current-controlled oscillator (CCO)-based A/D converters (ADCs) at a compact 4- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> pitch and a local digital processing unit (LDPU) performing affine scaling and ReLU operations. A frequency-linearization technique for CCO is introduced, which increases the maximum CCO frequency beyond 3 GHz, while ensuring accurate on-chip matrix–vector multiplications (MVMs). Moreover, the design and functionality of the digital ADC calibration procedure is described in detail and the MVM accuracy is quantified. Finally, the measured classification accuracies of deep learning (DL) inference applications on the MNIST and CIFAR-10 datasets, when two IMC cores are employed, are presented. For a performance density of 1.59 TOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , a measured energy efficiency of 10.5 TOPS/W, at a main clock frequency of 1 GHz, is achieved.

Multi-level phase-change memory with ultralow power consumption and resistance drift

By controlling the amorphous-to-crystalline relative volume, chalcogenide phase-change memory materials can provide multi-level data storage (MLS), which offers great potential for high-density storage-class memory and neuro-inspired computing. However, this type of MLS system suffers from high power consumption and a severe time-dependent resistance increase (“drift”) in the amorphous phase, which limits the number of attainable storage levels. Here, we report a new type of MLS system in yttrium-doped antimony telluride, utilizing reversible multi-level phase transitions between three states, i.e., amorphous, metastable cubic and stable hexagonal crystalline phases, with ultralow power consumption (0.6–4.3 pJ) and ultralow resistance drift for the lower two states (power-law exponent < 0.007). The metastable cubic phase is stabilized by yttrium, while the evident reversible cubic-to-hexagonal transition is attributed to the sequential and directional migration of Sb atoms. Finally, the decreased heat dissipation of the material and the increase in crystallinity contribute to the overall high performance. This study opens a new way to achieve advanced multi-level phase-change memory without the need for complicated manufacturing procedures or iterative programming operations.

Crystallization Properties of Al-Sb Alloys for Phase Change Memory Applications

Material properties of Al-Sb binary alloy thin films deposited under ultra-high vacuum conditions were studied for multi-level phase change memory applications. Crystallization of this alloy was shown to occur in the temperature range of 180 °C–280 °C, with activation energy >2 eV. X-ray diffraction (XRD) from annealed alloy films indicates the formation of two crystalline phases, (i) an Al-doped A7 antimony phase, and (ii) a stable cubic AlSb phase. In-situ XRD analysis of these films show the AlSb phase crystalizes at a much higher temperature as compared to the A7 phase after annealing of the film to 650 °C. Mushroom cell structures formed with Al-Sb alloys on 120 nm TiN heater show a phase change material resistance switching behavior with reset/set resistance ratio >1000 under pulse measurements. TEM and in situ synchrotron XRD studies indicate fine nucleation grain sizes of ∼8–10 nm, and low elemental redistribution that is useful for improving reliability of the devices. These results indicate that Te-free Al-Sb binary alloys are possible candidates for analog PCM applications.

Three Resistance States Achieved by Nanocrystalline Decomposition in Ge‐Ga‐Sb Compound for Multilevel Phase Change Memory

AbstractPhase‐change memory (PCM), using the fast and reversible transition between crystal and glass to store binary data, is a promising candidate for next‐generation information storage and computing technologies. Recording more than one bit of information on each memory cell, known as multilevel cell (MLC) technology, can greatly increase the data density of PCMs. In this paper, the MLC capability in a phase change material Ge‐Ga‐Sb (GGS) is explored. Using the “SET” operation with increasing voltage amplitudes on this PCM cell in a 250 nm pillar structure device, three resistance levels are achieved and can be stabilized within large operating voltage windows, allowing large tolerance of SET voltage variation which may lead to the overlap of the neighboring resistance levels. It is discovered that the additional resistance level other than “0” and “1” is enabled by compositional phase separation in the nanocrystalline GGS, as revealed via atom probe tomography and electronic microscopy. The device also shows small resistance drift (ν = 0.025) in amorphous state, about four times lower than prototypical Ge‐Sb‐Te‐based PCMs, stabilizing it against time variation. Meanwhile, high thermal stability (Tc ≈ 300 °C) in GGS‐based device can also facilitate the practical applications in some extreme conditions.

Designing Multiple Crystallization in Superlattice-like Phase-Change Materials for Multilevel Phase-Change Memory

A multilevel phase-change memory device was successfully designed, which was fabricated using a Ge40Te60/Cr superlattice-like (SLL) structure. In the SLL films, a two-step phase change process is observed at elevated temperatures, which reveals the crystallization of Ge40Te60 (GT) and an interface-dominated formation of Cr2Ge2Te6 (CrGT). The bonding of Cr-Te and Ge-Ge is accompanied by the breaking of a Ge-Te bond, which is mainly in the Ge-rich GeTe4-nGen units. The formation of CrGT is related to the breaking apart of the edge-sharing octahedron in GT and Cr replacement at Ge sites. The crystalline GT acts as the crystallization precursors in the formation of the CrGT phase. The stable reversible two-step phase change can guarantee the reliability of the multilevel storage. The present work may shed light on the possible mechanism of the CrGT phase transition-based interfacial dynamic process. The designed multiple crystallization system demonstrates a potential for multilevel storage.

Ultra-Low Program Current and Multilevel Phase Change Memory for High-Density Storage Achieved by a Low-Current SET Pre-Operation

We have fabricated a pillar structure phase change memory (PCM) with the prototypical phase change material Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Sb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Te <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> . Using a Low Current SET (LCS) pre-operation, the devices can operate with an ultralow RESET current density and have multilevel cell (MLC) capability, and these features both contribute to high storage density. Specifically, the RESET current density is only 4.84 MA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which is lowest among all the CMOS compatible PCM devices, and this ultra-low RESET current density enables the possibility to link with a two-terminal selector for 3D cross-point application. Meanwhile LCS makes MLC operation of our PCM more stable with a low operating current. In summary, this LCS pre-operation can greatly increase the storage density both by enabling integration with selectors for 3D cross-point and by stabilizing MLC operation when maintaining the feature size of PCM devices.

Speeding Up the Write Operation for Multi-Level Cell Phase Change Memory with Programmable Ramp-Down Current Pulses.

Multi-level cell (MLC) phase change memory (PCM) can not only effectively multiply the memory capacity while maintaining the cell area, but also has infinite potential in the application of the artificial neural network. The write and verify scheme is usually adopted to reduce the impact of device-to-device variability at the expense of a greater operation time and more power consumption. This paper proposes a novel write operation for multi-level cell phase change memory: Programmable ramp-down current pulses are utilized to program the RESET initialized memory cells to the expected resistance levels. In addition, a fully differential read circuit with an optional reference current source is employed to complete the readout operation. Eventually, a 2-bit/cell phase change memory chip is presented with a more efficient write operation of a single current pulse and a read access time of 65 ns. Some experiments are implemented to demonstrate the resistance distribution and the drift.

High-performance and flexible photodetectors based on chemical vapor deposition grown two-dimensional In2Se3 nanosheets

Two-dimensional (2D) In2Se3 with unique optical and electrical properties has great potential in next generation optoelectronics and multilevel phase-change memories. Here, for the first time, we report high-performance rigid and flexible photodetectors based on chemical vapor deposition (CVD) grown 2D In2Se3. Both rigid and flexible 2D In2Se3 photodetectors show a broadband response range from ultraviolet (254 nm) to visible light (700 nm). High photoresponsivities of 578 and 363 A · W−1 are achieved using rigid and flexible 2D In2Se3 photodetectors, respectively, under 700 nm light illumination, which are higher than those of photodetectors based on mechanically exfoliated 2D In2Se3 and physical vapor deposition grown 2D In2Se3. Furthermore, flexible 2D In2Se3 photodetectors show good mechanical durability and photoresponse stability under repeated bending tests. A high and stable photoresponse provides an opportunity for CVD-grown 2D In2Se3 applications in flexible optoelectronic and photovoltaic devices.

GeTe/Sb4Te films: A candidate for multilevel phase change memory

In this paper, GeTe and Sb4Te layers were alternately deposited to form superlattice-like structure (SLL) for multilevel phase change memory (PCM). It is shown that SLL GeTe/Sb4Te film can realize a multilevel storage with various appropriate thickness ratios between GeTe and Sb4Te layers. The crystallization behavior of SLL GeTe/Sb4Te film can be tuned by the thickness ratios which is associated closely with the thermal stability. GeTe(4 nm)/Sb4Te(6 nm)-based device demonstrated the minimum voltage pulse for the RESET operation of 3.2 V-5 ns, suggesting the low power consumption in comparison with that of Ge2Sb2Te5 (4.1 V). An electric pulse as short as 5 ns can trigger different operations among three stable resistance states for GeTe(4 nm)/Sb4Te(6 nm)-based device, which can be explained by the asynchronous crystallization of GeTe and Sb4Te. These results demonstrate that SLL GeTe/Sb4Te films are promising candidate for multilevel phase-change memory.

Exploiting Approximate MLC-PCM in Low-Power Embedded Systems

Multi-level cell phase change memory (MLC-PCM), because of its very low leakage power and high density, is promising for embedded systems. Furthermore, for applications with inherent low sensitivity to errors, approximate write operations can be exploited in MLC-PCM to improve endurance and performance. However, data that reside in the approximate MLC-PCM for a rather long time without refreshing are prone to soft errors due to resistance drift phenomenon, while even for an application with inherent low sensitivity to errors, a high soft error rate can degrade its Quality of Result (QoR). The architecture-level approaches to decrease the drift effect incur considerable power overhead (about 100%), which is a prominent issue in embedded systems, and are dependent on the number of logic levels stored in the PCM cell (e.g., most of them are designed for 4LC-PCM). This article, taking a different approach, proposes a drift-aware frequency and voltage management to alleviate the drift-based soft-error rate. To this end, first we characterize the application data based on the degree of being exposed to the drift to identify the drift-prone application data. Then we assign the execution frequency and voltage to different regions of the application considering the drift. This frequency assignment speeds up the application regions wherein the drift-prone data are accessed to shorten the lifetime of the drift-prone data, thereby decreasing the soft error rate. An integer linear programming model implements our proposed Dynamic Voltage Frequency Scaling (DVFS). Also, the proposed approach is independent of the number of levels of PCM cells and can be applied to any MLC-PCM system. To evaluate the approach, the approximate MLC-PCM is simulated using empirical models and is integrated into a full-system simulator as data memory. The experimental results show that, by exploiting the approach, QoR is in the acceptable range, while its power overhead is about 84% (on average) less than that of the architecture-level approach.

HL-PCM: MLC PCM Main Memory with Accelerated Read

Multi-Level Cell Phase Change Memory (MLC PCM) is a promising candidate technology for DRAM replacement in main memory of modern computers. Despite of its high density and low power advantages, this technology seriously suffers from slow read and write operations. While prior works extensively studied the problem of slow write, this paper targets high read latency problem in MLC PCM and introduces an architecture mechanism to overcome it. To this end, we rely on the fact that reading different bits from an MLC cell takes different latencies, i.e., for a 2-bit MLC, reading its Most-Significant Bit (MSB) is fast, while reading its Least-Significant Bits (LSBs) is slower. We then propose Half-Line PCM (HL-PCM), a novel memory architecture that leverages this non-uniformity in reading MLC PCM’s content to send a requested memory block to the processor in different cycles–it sends half of a memory block to the processor ahead of the other half. If the processor requested a word belonging to the first half, it can resume its execution on receiving the first half, while the other half has not sent yet and scheduled to be received by the memory controller later. HL-PCM is easy and simple to implement, i.e., it needs minor modifications at memory controller, the search/evict policies at last level cache, as well as data layout in main memory. Our experimental results show that the proposed design improves the average memory access latency by 33–43 percent and program’s execution time by 23 percent, on average, while incurring negligible overhead at memory controller and PCM DIMM, in a 16-core chip multiprocessor (CMP) running memory-intensive benchmarks.