Multi-level Phase Change Memory Research Articles

Controllable multilevel resistance state of superlattice-like GaSb/Ge2Te films for ultralong retention phase-change memory

The superlattice-like (SLL) GaSb/Ge2Te multilayer thin films were proposed for multilevel ultralong-retention phase-change memory (PCM). Multiple resistance states can be achieved by tuning the thickness ratio between GaSb and Ge2Te layers. The intermediate resistance state could be maintained at a large temperature gap over a wide range from 270 to 355°C, which guarantee the substantial reliability of the multilevel storage. The high crystallization temperature and 10-years data-retention temperature indicate the high thermal stability of the GaSb/Ge2Te films. After crystallization, the density of the GaSb/Ge2Te multilayer thin films increased slightly. It is in favor of the high reliability for the multilevel PCM. The two crystallization processes and three resistance states support a multilevel storage in the GaSb/Ge2Te-based test cell. The multiple resistance states originate from the localization of the electronic states, which result from the disorder as a result of doping element migrating from neighbor layer. The minimum energy necessary for RESET operation of GaSb/Ge2Te (3.7×10−11J) is lower than that of Ge2Sb2Te5 (8.1×10−10J) cell. GaSb/Ge2Te-based cell exhibited lower power consumption, high thermal stability and fast switching speed, suggesting GaSb/Ge2Te being one of the potential materials for multilevel PCM.

Multilevel data storage in multilayer phase change material

Superlattice-like GaSb/Sb4Te phase change film was proposed for multilevel phase change memory with the feature of three stable resistance states. Two distinct transition temperatures of around 170 and 230 °C were observed in the superlattice-like GaSb/Sb4Te thin film. Under elevated temperature, the precipitated rhombohedral Sb phase was found in the Sb4Te layer, which was followed by the crystallization of rhombohedral Sb2Te3, whereas the GaSb layer remained almost in the amorphous state except the impinged Sb grains. The formation of percolation path for crystallization in the GaSb layer can account for the multilevel resistance states. For the GaSb/Sb4Te-based device, the reversibly electrical switching was realized under the electrical pulse as short as 10 ns, and the endurance was achieved at least 105 cycles among different resistance states.

Implementation of time-aware sensing technique for multilevel phase change memory cell

This paper introduces and tests a time-aware sensing scheme to overcome the drift issue in Multi-Level Phase Change Memory (MLPCM). Adaptive resistance thresholds are calculated based on statistical data to generate timely reference levels for comparison. Simulations are carried out utilizing MLPCM cell model that mimics the physical behavior of MLPCM cell. The simulation results were then compared against experimental data, and it was noted that simulation results of the used MLPCM model are in close agreement with the experimental data. Furthermore, the time aware sensing scheme provided an accurate reading of the stored bit values given that the timely reference levels successfully compensated for the drift phenomenon. Finally, an application of time aware sensing coupled with MLPCM was implemented, where MPLCM is used as memory element in a Look Up Table (LUT). The suggested MLPCM based LUT utilizes the density and reliability offered by MLPCM paired with the presented time aware sensing scheme.

Toward Multiple-Bit-Per-Cell Memory Operation With Stable Resistance Levels in Phase Change Nanodevices

Resistance drift of the amorphous states of multilevel phase change memory (PCM) cells is currently a great challenge for the commercial implementation of a reliable multiple-bit-per-cell memory technology. This paper reports observation of a stable intermediate state for a multilevel PCM cell that is achieved through nonuniform heating with a square current injection top electrode. Drift coefficient of the intermediate state is an order of magnitude lower than reset and has weaker temperature dependence. Using finite-element simulations and an analytical model for the subthreshold current–voltage characteristics, based on thermally activated hopping of charge carriers across Coulombic donor-like traps, we conclude that the defect density is two orders of magnitude larger in the intermediate state. We attribute the low drift coefficient of the intermediate state to a large number of stable interfacial defects which dominate the electron transport. Current findings give way to a more stable ultrahigh-density PCM device.

A 15 µm-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory

This paper presents a narrow-pitch readout circuit for multi-level phase change memory (PCM) employing an architecture of two-step 5 bit logarithmic ADC. A single-slope-architecture based fine ADC yields a 15 $\mu$ m-width compact single channel readout circuit for column parallel readout structure. A current-mode 2 bit flash ADC for coarse conversion and the pipelined architecture between the coarse and fine conversion enhance the readout rate up to 13 Mcells/sec. With the enhanced residue accuracy provided by the replica circuit of residue generator, the ADC achieves excellent linearity of 9.96 b (linear ADC equivalent). The integration-based residue generation effectively reduces circuit noise and yields 8.7 ENOB. The prototype chip was fabricated in a 65 nm CMOS process and the measured power consumption from a single channel readout circuit was 105 $\mu$ W at 13 Mcells/sec conversion rate at 1.2 V supply.

Balancing the Lifetime and Storage Overhead on Error Correction for Phase Change Memory.

As DRAM is facing the scaling difficulty in terms of energy cost and reliability, some nonvolatile storage materials were proposed to be the substitute or supplement of main memory. Phase Change Memory (PCM) is one of the most promising nonvolatile memory that could be put into use in the near future. However, before becoming a qualified main memory technology, PCM should be designed reliably so that it can ensure the computer system’s stable running even when errors occur. The typical wear-out errors in PCM have been well studied, but the transient errors, that caused by high-energy particles striking on the complementary metal-oxide semiconductor (CMOS) circuit of PCM chips or by resistance drifting in multi-level cell PCM, have attracted little focus. In this paper, we propose an innovative mechanism, Local-ECC-Global-ECPs (LEGE), which addresses both soft errors and hard errors (wear-out errors) in PCM memory systems. Our idea is to deploy a local error correction code (ECC) section to every data line, which can detect and correct one-bit errors immediately, and a global error correction pointers (ECPs) buffer for the whole memory chip, which can be reloaded to correct more hard error bits. The local ECC is used to detect and correct the unknown one-bit errors, and the global ECPs buffer is used to store the corrected value of hard errors. In comparison to ECP-6, our method provides almost identical lifetimes, but reduces approximately 50% storage overhead. Moreover, our structure reduces approximately 3.55% access latency overhead by increasing 1.61% storage overhead compared to PAYG, a hard error only solution.

Non-Binary Orthogonal Latin Square Codes for a Multilevel Phase Charge Memory (PCM)

This manuscript proposes non-binary orthogonal Latin square (OLS) codes that are amenable to a multilevel phase change memory (PCM). This is based on the property that the proposed ( n symbols, k symbols) t -symbol error correcting code uses the same H matrix as an ( n bits, k bits) binary t -bit error correcting OLS code. The new codes are shown to have a shorter check bit length and better probability in encoding/decoding than conventional binary OLS codes. Extensive results are provided for assessment and comparison. The proposed codes are also shown to be always better than the matrix codes, i.e. independently of the metric and the parameters employed in the comparison.

Phase Change Memory Write Cost Minimization by Data Encoding

Phase change memory (PCM) is a promising next generation nonvolatile memory. Despite the currently popular charge-based storage techniques, PCM leverages a much more scalable thermal-resistive mechanism that enables sub-10 nm feature sizes. To realize PCM's potential, there are a number of technical challenges that need to be addressed, including limited wear endurance and high energy consumption of bit writes. Our work introduces a novel set of tools and methodologies for encoding data on PCM that optimizes its write performance. We develop a framework which exploits asymmetries in PCM read/write. We show that this coding problem is NP-complete. To provide a tractable solution, we propose two different methods: the first uses integer linear programming, and the second leverages dynamic programming to find an approximation of the optimal solution. Our methods target both single and multi-level cell PCM and can be directly applied to any asymmetric nonvolatile memory with bit-level accessibility. We further optimize our codes by leveraging data distributions. We devise a low-overhead architecture for the encoder module which can be easily integrated within the existing computer memory architecture. We demonstrate the applicability, low overhead, and efficiency of our proposed framework with extensive evaluations.

Multi-Level Lateral Phase Change Memory Based on N-Doped Sb70Te30 Super-Lattice like Structure

Lateral phase change memory (PCM) has attracted a lot of interest due to its simpler fabrication process and lower current. Researchers are trying to increase the storage capacity of lateral PCM. This paper proposed a novel super-lattice like (SLL) structure for lateral PCM to achieve multi-level storage. Lateral PCM with SLL structure incorporated with N-doped Sb70Te30 and ZnS-SiO2 has been fabricated and tested. Both tested static I-V curve and dynamic pulse mode R-V curve show multi states existing in the device. Electrical and thermal simulations have been done for this device. Simulation results show that different resistance level can be found in this device with different states of phase change bridges. With increasing periods of SLL structure, more states can be achieved.

A Model for Multilevel Phase-Change Memories Incorporating Resistance Drift Effects

Phase change memories are emerging as a most promising technology for future nonvolatile, solid-state, electrical storage. However, to compete effectively in mainstream storage applications, a multilevel cell capability is most desirable. Unfortunately, phase-change memories exhibit a temporal drift in programmed resistance (and in threshold switching voltage) which appears to be a fundamental and universal property of the amorphous or partially amorphous phase. Phase-change device models should therefore include these drift effects in a realistic way so that circuit and systems designers can assess the likely performance of multilevel phase-change memories in a variety of potential applications. In this paper, therefore, we present a comprehensive SPICE-based model for phase-change devices that includes the capability for programming into multiple resistance levels, the prediction of the drift of cell resistance (and threshold voltage) with time, and the capability for modeling the randomness inherent to the resistance drift phenomenon. Simulations of multilevel programming and drift phenomena using the model are presented and compared to experimental results, with which there is very good agreement.

Approximate Storage in Solid-State Memories

Memories today expose an all-or-nothing correctness model that incurs significant costs in performance, energy, area, and design complexity. But not all applications need high-precision storage for all of their data structures all of the time. This article proposes mechanisms that enable applications to store data approximately and shows that doing so can improve the performance, lifetime, or density of solid-state memories. We propose two mechanisms. The first allows errors in multilevel cells by reducing the number of programming pulses used to write them. The second mechanism mitigates wear-out failures and extends memory endurance by mapping approximate data onto blocks that have exhausted their hardware error correction resources. Simulations show that reduced-precision writes in multilevel phase-change memory cells can be 1.7 × faster on average and using failed blocks can improve array lifetime by 23% on average with quality loss under 10%.

A Temperature Tracking Read Reference Current and Write Voltage Generator for Multi-Level Phase Change Memories

A Temperature Tracking Read Reference Current and Write Voltage Generator for Multi-Level Phase Change Memories

Crystalline–Crystalline Phase Transformation in Two-Dimensional In2Se3 Thin Layers

We report, for the first time, the fabrication of single-crystal In2Se3 thin layers using mechanical exfoliation and studies of crystalline-crystalline (α → β) phase transformations as well as the corresponding changes of the electrical properties in these thin layers. Particularly, using electron microscopy and correlative in situ micro-Raman and electrical measurements, we show that, in contrast to bulk single crystals, the β phase can persist in single-crystal thin layers at room temperature (RT). The single-crystal nature of the layers before and after the phase transition allows for unambiguous determination of changes in the electrical resistivity. Specifically, the β phase has an electrical resistivity about 1-2 orders of magnitude lower than the α phase. Furthermore, we find that the temperature of the α → β phase transformation increases by as much as 130 K with the layer thickness decreasing from ~87 nm to ~4 nm. These single-crystal thin layers are ideal for studying the scaling behavior of the phase transformations and associated changes of the electrical properties. For these In2Se3 thin layers, the accessibility of the β phase at RT, with distinct electrical properties than the α phase, provides the basis for multilevel phase-change memories in a single material system.

Ga19Sb81 film for multi-level phase-change memory

We studied Ga19Sb81 film deposited on SiOx/Si(100) by RF co-sputtering using GaSb and Sb targets aiming for applications in multi-level phase-change memory. Crystallization temperature (Tx) is 228°C–235°C determined by electrical resistance versus temperature measurements at various heating rates. The dramatic resistance drop is attributed to increased carrier concentration based on Hall measurements. The films show p-type conduction behavior at all temperature regimes. The temperature for ten-year failure-time (T10y) and the activation energy of crystallization (Ea) is 156°C and 4.2eV, respectively, as deduced using Arrhenius plots from as-deposited films. The two-step drop in resistance is attributed to the two-step phase formation as depicted by X-ray diffractometry. Density changes before and after crystallization is 5.3% (Ge2Sb2Te5: 9.5%) as analyzed by the X-ray reflectivity method. Memory switching is carried out by using test cells with a via hole size of 600nm. Set and reset processes can be achieved by using pulse widths of 20–100ns. The cycling test showed performance at least 104 set–reset times. Furthermore, two stable set states are routinely achieved by controlling set voltages. The two states can be operated at least 102cycles steadily with resistance ratios ~5 and ~22 times, respectively. The two set states arise from the formation of two phases (Sb then GaSb) during set operations.

×10 Fast write, 80% energy saving temperature controlling set method for multi-level cell phase change memories to solve the scaling blockade

This paper presents a new set method with temperature control to reduce both energy dissipation and write time of multi-level cell (MLC) phase change memories (PCMs). Since the set energy of PCM is quite larger than reset due to long set time, reducing the set energy is a critical issue to realize MLC PCM. Moreover, this paper shows the set time and energy become longer and lager as the diameter of a tungsten heater is scaled down due to thermal dissipation. To solve these problems, this paper proposes a unique set pulse which combines two pulses: the 1st pulse is high voltage and short width and the 2nd pulse is low voltage and long width. The 1st pulse contributes to faster set time and the 2nd pulse controls the crystallization of GST film. As a result, ∼80% of energy saving and ∼10-times fast write speed are achieved for a 90nm MLC PCM. The proposed set method overcomes the scaling blockade due to thermal dissipation and is essential for a nano-scale MLC PCM.

Multi-Level Phase Change Memory Cells with SiN or Ta2O5Barrier Layers

Multi-Level Phase Change Memory Cells with SiN or Ta₂O₅Barrier Layers

Multi-Level Phase Change Memory Cells with SiN or Ta2O5 Barrier Layers

This work compares the effects of SiN and Ta2O5 barrier layers in a multi-level phase change random access memory (PCRAM) cell. The PCRAM cell comprises a phase change material stack between a top and a bottom electrode. The phase change material stack comprises a nitrogen-doped Ge2Sb2Te5 (NGST) layer on top of a thin barrier layer on an undoped GST layer. The thermal conductivity and electrical resistivity of the barrier layer affect multi-level switching performance in terms of endurance as well as power consumption. Extensive electrical characterization was performed on these PCRAM multi-level devices. Thermal analysis was also performed to investigate the thermal efficiency of each barrier layer. It was observed that for a constant barrier layer thickness of 1.5 nm, the endurance of the multi-level device with the SiN barrier layer was better than that with the Ta2O5 barrier layer; however, the multi-level device with the Ta2O5 barrier layer had a lower power consumption than that with the SiN barrier layer.

Multi-level phase change memory devices with Ge2Sb2Te5 layers separated by a thermal insulating Ta2O5 barrier layer

This work investigates multi-level phase change random access memory (PCRAM) devices comprising two Ge2Sb2Te5 (GST) layers sandwiching a thermal insulating Ta2O5 barrier layer. The PCRAM cell comprises a phase change material stack between a top and a bottom electrode. The phase change material stack comprises a nitrogen doped GST (NGST) layer on a thin Ta2O5 barrier layer on an undoped GST layer. It is demonstrated that one of the phase change layers in the GST stack can be selectively amorphized by using a voltage pulse. This enables multi-level resistance switching. The differences in resistivities, as well as the different melting and crystallization temperatures of both the NGST and GST layers, contribute to the multi-level switching dynamics of the PCRAM device. The thermal conductivity of Ta2O5 with respect to GST is also another factor influencing the multi-level switching. Extensive electrical characterization of the PCRAM devices was performed. Thermal analysis was used to examine the physics behind the multi-level switching mechanism of these devices.

Non-resistance-based cell-state metric for phase-change memory

In phase-change memory (PCM), low-field electrical resistance is typically used to quantify the programmed cell state. However, this metric has several disadvantages. First, it exhibits temporal drift, which is a significant challenge for realizing multilevel PCM. Moreover, because of cell-geometry effects, this metric saturates after a certain point and thus masks the fact that the amorphous size increases with increasing input power. Finally, the resistance is typically measured as the current for a fixed bias voltage, which adversely affects the signal-to-noise ratio at high resistance values. A new metric for the programmed state in a PCM cell is proposed that has significant advantages over the resistance metric in all these aspects and is more representative of the fundamental programmed entity, which is the amorphous/crystalline phase configuration in the PCM cell. Analytical and experimental results are presented that demonstrate the efficacy of the proposed metric.

A Time-Aware Fault Tolerance Scheme to Improve Reliability of Multilevel Phase-Change Memory in the Presence of Significant Resistance Drift

Because of its promising scalability potential and support of multilevel per cell storage, phase-change memory has become a topic of great current interest. However, recent studies show that structural relaxation effect makes the resistance of phase-change material drift over the time, which can severely degrade multilevel per cell phase-change memory storage reliability. This makes powerful memory fault tolerance solutions indispensable, where error correction code (ECC) will play an essential role. This work aims to develop fault tolerance solutions that can effectively compensate memory cell resistance drift. First, based upon information-theoretical study, we show that conventional use of ECC, which is unaware of memory content lifetime, can only achieve the performance with a big gap from the information-theoretical bounds. This motivates us to study the potential of time-aware memory fault tolerance, where the basic idea is to keep track the memory content lifetime and use this lifetime information to accordingly adjust how memory cell resistance is quantized and interpreted for ECC decoding. Under this time-aware fault tolerance framework, we study the use of two types of ECCs, including classical codes such as BCH that only demand hard-decision input and advanced codes such as low-density parity-check (LDPC) codes that demand soft-decision probability input. Using hypothetical four-level per cell and eight-level per cell phase-change memory with BCH and LDPC codes as test vehicles, we carry out extensive analysis and simulations, which demonstrate very significant performance advantages of such time-aware memory fault tolerance strategy in the presence of significant memory cell resistance drift.