Exploiting Approximate MLC-PCM in Low-Power Embedded Systems

Abstract

Multi-level cell phase change memory (MLC-PCM), because of its very low leakage power and high density, is promising for embedded systems. Furthermore, for applications with inherent low sensitivity to errors, approximate write operations can be exploited in MLC-PCM to improve endurance and performance. However, data that reside in the approximate MLC-PCM for a rather long time without refreshing are prone to soft errors due to resistance drift phenomenon, while even for an application with inherent low sensitivity to errors, a high soft error rate can degrade its Quality of Result (QoR). The architecture-level approaches to decrease the drift effect incur considerable power overhead (about 100%), which is a prominent issue in embedded systems, and are dependent on the number of logic levels stored in the PCM cell (e.g., most of them are designed for 4LC-PCM). This article, taking a different approach, proposes a drift-aware frequency and voltage management to alleviate the drift-based soft-error rate. To this end, first we characterize the application data based on the degree of being exposed to the drift to identify the drift-prone application data. Then we assign the execution frequency and voltage to different regions of the application considering the drift. This frequency assignment speeds up the application regions wherein the drift-prone data are accessed to shorten the lifetime of the drift-prone data, thereby decreasing the soft error rate. An integer linear programming model implements our proposed Dynamic Voltage Frequency Scaling (DVFS). Also, the proposed approach is independent of the number of levels of PCM cells and can be applied to any MLC-PCM system. To evaluate the approach, the approximate MLC-PCM is simulated using empirical models and is integrated into a full-system simulator as data memory. The experimental results show that, by exploiting the approach, QoR is in the acceptable range, while its power overhead is about 84% (on average) less than that of the architecture-level approach.