Pattern-Aware Encoding for MLC PCM Storage Density, Energy Efficiency, and Performance Enhancement

Abstract

With the scaling limitations and increasing leakage power of the existing charge-based memories, next-generation memory technologies to overcome the issues are in development. Among the various emerging memories, phase change memory (PCM) is considered as a promising candidate due to its scalability potential and negligible leakage power. For enhanced storage density, the multilevel cell (MLC) operation has been proposed for PCM. This, however, comes at cost of poor reliability, write energy increase and performance degradation. Unlike DRAM, the MLC PCM has a much higher soft error rate due to the resistance drift phenomenon. Error correction code (ECC) schemes can be utilized to improve the MLC PCM reliability, however, this would lead to a lower storage density and an increase in write energy and latency. The iterative programming required for the MLC PCM also degrades its energy efficiency and performance. This paper introduces a simple yet effective encoding scheme to mitigate the problems of the MLC PCM. By using a simple XOR-based encoding, the proposed architecture minimizes the most drift-prone state in the data. The method divides the original data into several encoding blocks and analyzes initial pattern frequencies for each 2-bit pattern. Based on the initial pattern frequencies, the inputs for the XOR encoding are selected that result in minimal frequency of the drift-prone state. This considerably enhances the MLC PCM reliability, leading to a high storage density with a reduced ECC overhead. The energy efficiency and performance are also improved due to reduction in iterative current pulses and ECC overhead. The simulation results show a reduction of about $10^{5}$ X in soft error rate. The improvements in energy efficiency and performance over the conventional 4-level cell (4LC) PCM are 11.5% and 31.9%, respectively.