Multi-level phase-change behaviors of Ge2Sb2Te5/Sb7Se3 bilayer films and a design rule of multi-level phase-change films

Abstract

Multi-level phase-change (MLPC) memory can not only further raise the storage density of high-density phase-change memory, but also have significant applications in neuromorphic computing. However, acquisitions of MLPC materials are very challenging. MLPC is only observed in a small number of phase-change materials and can’t be designed determinately because the mechanism of MLPC emergence has been understood incompletely. Here, we investigate phase-change behaviors of six Ge2Sb2Te5(x nm)/Sb7Se3 (60-x nm) bilayer films with x = 5, 10, 15, 20, 35, and 50. Three-level phase-change memory is observed for five bilayer films with x < 50, but not for one with x = 50, revealing the dependence of MLPC memory on the thickness ratio of two constituent layers composing bilayer films. A parallel resistance model is proposed to describe the measured sheet resistance of bilayer films and can be used to explain the thickness-ratio dependence of three-level phase-change memory very well. Subsequently, a design rule for MLPC memory films is given out unambiguously. Based on the parallel resistance model, MLPC memories are simulated for bilayer and trilayer films. Three-level memory indeed appears in bilayer films only when the design rule is met, confirming the validity of our design rule. Four-level memory is predicted in trilayer films as the design rule is obeyed.