Double-gate Research Articles

Correction to: Quantization Effect in N-Channel Inversion Mode Si, In0.53Ga0.47As and Ge Based Double Gate MOSFET Using Quasi-Static Capacitance–Voltage Characteristics for Upcoming Sub 10 nm Technology Node

Correction to: Quantization Effect in N-Channel Inversion Mode Si, In0.53Ga0.47As and Ge Based Double Gate MOSFET Using Quasi-Static Capacitance–Voltage Characteristics for Upcoming Sub 10 nm Technology Node

Controllable Synthesis of Transferable Ultrathin Bi2Ge(Si)O5 Dielectric Alloys with Composition-Tunable High-κ Properties.

Two-dimensional (2D) alloys hold great promise to serve as important components of 2D transistors, since their properties allow continuous regulation by varying their compositions. However, previous studies are mainly limited to the metallic/semiconducting ones as contact/channel materials, but very few are related to the insulating dielectrics. Here, we use a facile one-step chemical vapor deposition (CVD) method to synthesize ultrathin Bi2SixGe1-xO5 dielectric alloys, whose composition is tunable over the full range of x just by changing the relative ratios of the GeO2/SiO2 precursors. Moreover, their dielectric properties are highly composition-tunable, showing a record-high dielectric constant of >40 among CVD-grown 2D insulators. The vertically grown nature of Bi2GeO5 and Bi2SixGe1-xO5 enables polymer-free transfer and subsequent clean van der Waals integration as the high-κ encapsulation layer to enhance the mobility of 2D semiconductors. Besides, the MoS2 transistors using Bi2SixGe1-xO5 alloy as gate dielectrics exhibit a large Ion/Ioff (>108), ideal subthreshold swing of ∼61 mV/decade, and a small gate hysteresis (∼5 mV). Our work not only gives very few examples on controlled CVD growth of insulating dielectric alloys but also expands the family of 2D single-crystalline high-κ dielectrics.

Spacer effects on the performance of MoTe2/MoSe2 and MoTe2/WSe2 heterostructure double gate MOSFET

In this work, the spacer effects (both low and high-k) on the dc and noise characteristics of heterostructure molybdenum ditelluride (MoTe2/MoSe2 and MoTe2/WSe2) double gate (DG) MOSFET is analyzed. To study the device characteristics, a hybrid methodology that uses both QuantumWise ATK and Sentaurus TCAD tool is used. The performance metrics of the device such as on-current (Ion), Ion/Ioff ratio, subthreshold swing (SS), threshold voltage are obtained. The noise performance of the device is also studied (with/without spacer) using impedance field method. Noise parameters such as noise power spectral density (SID) and noise figure (function of both frequency and bias) has also been simulated and noise components such as G-R noise, flicker noise and white noise are obtained. The simulation results shows that the introduction of spacer material enhances the dc performance of the device and influences its noise characteristics.

Recent Experimental Breakthroughs on 2D Transistors: Approaching the Theoretical Limit

AbstractSince Si‐based Moore's law is physically limited, 2D semiconductors are proposed as successors to continue shrinking the transistor size for more Moore electronics. However, limited by experimental technology bottlenecks, the theoretical predicted superiorities of the 2D transistors over the state‐of‐the‐art Si transistors have been lacking concrete evidence for a decade. In this review, recent exciting experimental breakthroughs for 2D transistors are presented, including gate length miniaturization to a sub‐1 nm limit, electrode contact optimization to the resistance quantum limit, high‐quality dielectric fabrication with an equivalent oxide thickness to sub‐0.5 nm, novel architecture form (2D fin field‐effect transistor), and back‐end‐of‐line integration of directly grown 2D materials on Si complementary metal‐oxide‐semiconductor circuits. Remarkably, an ultrashort channel, Ohmic contact, ballistic transport, and ultrathin dielectric layer are simultaneously satisfied in the 2D InSe transistor, and device performances approaching the theoretical limit are observed. The measured key figures of merit of the ideal 2D InSe transistor are comparable to or even surpass those of the Si transistors. Finally, the challenges and outlook on more Moore electronics based on 2D transistors are highlighted.

Optimization of Dual Material Based Dielectric Modulated Heterojunction Double Gate Tunnel FETs with Noise Reduction Analysis for High Frequency Applications

Optimization of Dual Material Based Dielectric Modulated Heterojunction Double Gate Tunnel FETs with Noise Reduction Analysis for High Frequency Applications

Design and Evaluation of a Double-Gate Tunnel Field Effect Transistor for the Detection of Breast Cancer Cells

This research paper investigates the application of a Double Gate (DG) Tunnel Field-Effect Transistor (DG-TFET) for the detection of cell lines derived from breast cancer tissue, namely Hs578T, MDA-MB-231, MCF-7, and T47D. The device incorporates two nanocavities positioned beneath the two gate electrodes, significantly enhancing detection capabilities. The study emphasizes the differentiation between healthy non-tumorigenic cells (MCF-10A) and breast cancer-derived cell lines by incorporating gate engineering into the TFET. Furthermore, the research explores the impact of changes in dielectric values specific to different breast malignant cell types on the biosensor's detection capabilities. Additionally, the investigation delves into the influence of variations in device geometry, including cavity dimensions and dielectric layer thickness, on critical parameters such as drain current sensitivity, transconductance sensitivity, and ION/IOFF sensitivity. Sensitivity analysis concerns drive current, ION/IOFF ratio, threshold voltage (Vth), and transconductance. The structural design of the device is tailored to facilitate array-based diagnosis and screening of cell lines derived from breast cancer tissue. This design offers several advantages, including a simplified transduction process, compatibility with CMOS processes, cost-effectiveness, reproducibility, and adjustable electrical responses. The researchers employed ATLAS, a two-dimensional (2D) device simulator from Silvaco, to model and define the device structure. The numerical simulations validate the device's performance, demonstrating favorable ON-OFF transition profiles.

Leaky-integrate-fire neuron based on vertically extended drain Si[formula omitted]Ge[formula omitted] source TFET: Ultra-energy-efficient and high speed design

This article investigates the performance of a vertically extended drain double gate Si1−x Gex source tunnel field effect transistor (VD-DG-Si1−x Gex S-TFET) as a leaky integrate-and-fire (LIF) neuron. The proposed VD-DG-Si1−x Gex S-TFET structure has been designed and optimized by deploying the commercially available Silvaco TCAD. The LIF neuron using VD-DG-Si1−x Gex S-TFET requires a low spiking threshold voltage (i.e. 0.20 V) which is 5x, 3x, 5x, 1.3x, 1.55x, 7.5x, and 1.44x times less in comparison to MOSFET, Bulk FinFET, phase change device, SOI MOSFET, DG-JLFET, silicon nanowire, and DL-TFET silicon neuron. The proposed device based neuron demonstrates the least spiking energy (177 ZJ) reported to date which is 18192 times less as compared to BTBT based PDSOI MOSFET neuron. The threshold value of current is achieved at 0.20 V drain voltage which is 15x, 14x, 10x, and 1.5x less as compared to FinFET, PD-SOI MOSFET, LBIMOS, and DL-TFET, respectively. Moreover, the effects of gate metal work function, germanium mole fraction, and temperature on the spike current variations have also been investigated. Here, impact ionization is a key method for generating a neuron spike due to holes accumulated in the potential well of VD-DG-Si1−xGex S-TFET. In addition, a LIF neuron based on VD-DG-Si0.5Ge0.5 S-TFET device exhibits a 9 THz spiking frequency which is approximately 12 times higher than real nerves present in the human body. This work shows a remarkable reduction in the power consumption and the proposed device neuron is a potential start-up solution for a large scale spiking neural networks (SNN) implementation because of its better performance and compact circuitry.

Analytical modeling of drain current for DG-Graphene Nanoribbon Vertical Tunnel FET

The semi-classical current transport model is used in this study to examine the drain current model for Double-Gate (DG) Dual-Material-Gate (DMG) Graphene-Nanoribbon (GNR) Vertical TFETs. It takes into account the contact potential (VGS, VDG), the impact of the oxide thickness (tOX), and the carrier mobility (μ). The device’s channel length is 50 nm, and the energy bandgap is 0.26 eV when the GNR ribbon width is 10 nm. The bandgap varies with the GNR ribbon width. The data from the simulation of TCAD tools are compared to an analytical result of the drain current. The current transport model shows good agreement. It is clear that a GNR with a 5 nm width can switch ON and OFF at 0.5 V drain voltage, which shows low power bias operation. The suggested GNR-TFET is capable of producing an average subthreshold current of 16 mV/Dec, 1.74 × 10−4 A/μm on-state current, and 1.66 × 10−18 A/μm off-state current. The exceptional performance is made possible by the narrow bandgap, high mobility, and two-dimensional (2-D) nature of GNR.

Design and analysis of logic circuits based on 8 nm double gate MOSFET

Design and analysis of logic circuits based on 8 nm double gate MOSFET

A Mg2Si/Si heterojunction based dielectric modulated dopingless TFET biosensor for label free detection

In this work, we contrasted the potential of Mg2Si/Si heterojunction-based dopingless (DL) double gate tunnel field effect transistor (DGTFET) with conventional (C)-DL-DGTFET. The simulation results exhibit excellent capabilities of Mg2Si source DL-DGTFET in terms of electrical properties, that are ION, ION/IOFF, electron tunnelling rate, Vth and SS in comparison to C-DL-TFET. A remarkable improvement of 77.5 % and 81.3 % is observed while computing Vth and SS, in the case of Mg2Si source DL-DGTFET. For that reason, to avail most advantage of Mg2Si/Si heterojunction, the proposed device with similar specifications and dimensions is critically analysed for biosensing applications. Dual cavities (20 nm x 5 nm) are carved underneath gate electrodes near source channel junction to grab the biomolecules. The proposed biosensor (Mg2Si source DL-DGTFET) exhibits significant sensitivity results for both charged (deoxyribonucleic acid (DNA)) and uncharged (neutral) biomolecules. Also, we have reported an impact on biosensor sensitivity with variation in the height of nanocavity (tbio). The effect of steric hindrance on sensitivity is analysed by considering four step profiles - increasing, decreasing, convex and concave. The result reveals the competency of Mg2Si/Si heterojunction DL-DGTFET in terms of overall device sensitivity.

Double-gate structure enabling remote Coulomb scattering-free transport in atomic-layer-deposited IGO thin-film transistors with HfO2 gate dielectric through insertion of SiO2 interlayer

In this paper, high-performance indium gallium oxide (IGO) thin-film transistor (TFT) with a double-gate (DG) structure was developed using an atomic layer deposition route. The device consisting of 10-nm-thick IGO channel and 2/48-nm-thick SiO2/HfO2 dielectric was designed to be suitable for a display backplane in augmented and virtual reality applications. The fabricated DG TFTs exhibit outstanding device performances with field-effect mobility (μFE) of 65.1 ± 2.3 cm2V−1 s−1, subthreshold swing of 65 ± 1 mVdec−1, and threshold voltage (VTH) of 0.42 ± 0.05 V. Both the (μFE) and SS are considerably improved by more than two-fold in the DG IGO TFTs compared to single-gate (SG) IGO TFTs. Important finding was that the DG mode of IGO TFTs exhibits the nearly temperature independent μFE variations in contrast to the SG mode which suffers from the severe remote Coulomb scattering. The rationale for this disparity is discussed in detail based on the potential distribution along the vertical direction using technology computer-aided design simulation. Furthermore, the DG IGO TFTs exhibit a greatly improved reliability with negligible VTH shift of − 0.22 V under a harsh negative bias thermal and illumination stress condition with an electric field of − 2 MVcm−1 and blue light illumination at 80 °C for 3600 s. It could be attributed to the increased electrostatic potential that results in fast re-trapping of the electrons generated by the light-induced ionization of deep level oxygen vacancy defects.

A New Approach to Design of Cost-Efficient Reversible Quantum Dual-Full Adder and Subtractor

This paper proposed the design and development of reversible cost-efficient innovative quantum dual-full adder and subtractor or QD-FAS circuit using quantum gate. The proposed circuit can be used as full adder and full subtractor simultaneously, which is designed using double Peres gate or DPG and Feynman gate or FG. The quantum cost, garbage output and constant input of the QD-FAS is 8, 1 and 1. Which is better w.r.t previously reported work. The QD-FAS circuit, as proposed, includes shared sum and difference terminals, as well as a carry-out and a borrow output terminal. Notably, this innovation showcases a remarkable 27.27% reduction in quantum cost. The improvement in garbage output is even more striking, showing a 50% enhancement. When assessing the overall advancement in quantum cost, it falls within the range of 27.27% to 66.66%. To confirm the viability of this design, extensive testing is carried out using the IBM Qiskit simulator. This design holds significant importance in a variety of applications, including quantum computing, cryptography, and the realm of reversible Arithmetic Logic Units (ALU).

Logic-in-memory application of ferroelectric-based WS2-channel field-effect transistors for improved area and energy efficiency

In this study, we applied ferroelectrics to the gate stack of Field Effect Transistors (FETs) with a 2D transition-metal dichalcogenide (TMDC) channel, actively researching for sub-2nm technology node implementation. Subsequently, we analyzed the circuit characteristics of Logic-in-Memory (LiM) operation and utilized LiM features after applying ferroelectrics to achieve a single-device configuration. Based on well-calibrated simulations, we performed compact modeling in a circuit simulator to depict the temperature-dependent electrical characteristics of ferroelectric FETs with a double gate structure and 2D channel (DG 2D-FeFET) in sub-2nm dimensions. Through this, we have confirmed that the 2D FeFET-based LiM technology, designed for the 2 nm technology node, exhibits superior characteristics in terms of delay, power/energy consumption, and circuit area under all temperature conditions, compared to the conventional CMOS technology based on 2D FETs. This verification serves as proof of the future technological potential of 2D-FeFET in extremely scaled-down technology nodes.

A novel 4H–SiC IGBT with double gate PMOS for improving the switch controllability and FBSOA

In this work, a 4H–SiC insulated-gate bipolar transistor (IGBT) with double gate PMOS (DGPMOS) is proposed. In the on-state, DGPMOS IGBT can form a hole barrier, thus reducing the on-state voltage (VON). During the turn-on and turn-off transients, DGPMOS IGBT can form the extra hole extraction paths. This helps to reduce the turn-off loss (Eoff) and the gate displacement current (IG_dis). The simulation results show that compared with GS IGBT, the VON of DGPMOS IGBT is decreased by 58.04% under the same Eoff. Compared with PMOS IGBT, DGPMOS IGBT achieves better controllability in turn-on dIC/dt and peak turn-on current (Imax). At the same turn-on loss (Eon), the maximum reverse recovery dVKA/dt is lowered by 26.67%, and the electromagnetic interference (EMI) noise is suppressed. In addition, because DGPMOS IGBT has a small saturation current density (Jsat), its forward bias safe operating area (FBSOA) is greatly improved.

Source engineered TFET for digital inverters application

This article delves into a performance evaluation of source engineered asymmetric Tunnel Field Effect Transistors using Sentaurus TCAD. The focus of this analysis centers around Single and Double gate extended Source TFET (SG-ESTFET and DG-ESTFET) device configurations. The study emphasizes the reliability of these devices for circuit applications taking in account interface trap charges. Various digital inverters based on the aforementioned TFET devices are designed, showcasing their potential utility in terms of different delay parameters. Additionally, the article explores transient characteristics and notes the occurrence of undershoot when interface trap charges are present at oxide-semiconductor interfaces. Notably, the findings indicate that DG-ESTFET surpasses SG-ESTFET in mitigating undershoot, and the measured propagation delay is reported to be 9 ps.

Impact of on-chip gate voltage on the electric properties of NbTiN superconducting nanowire transistor

In this work, the gate modulation characteristics of superconducting nanowire transistors (SNTs) were investigated under different on-chip gate voltage configurations. By fabricating NbTiN-SNTs with symmetric side gate, we studied the critical current suppression of SNTs under single, opposite, and double voltage gate. We figure out that the gate voltage and leakage current can be adjusted by the gate configuration. Moreover, it revealed an approximately twofold increase in modulation voltage for the opposite gate configuration as compared to the single gate configuration, implying a possible electric field tuned superconductivity. When simultaneously apply voltage on both gates, the onset and offset voltages kept unchanged, but the leakage current is then two times higher than that of single gate. In addition, under all these three types of gate configuration, the suppression of superconductivity coincided with the onset of leakage current, suggesting a potential charge injection mechanism. Our findings demonstrate that both the electric field and charge injection play important roles on the suppression of superconductivity in SNTs, which also contributes to the further optimization and applications of SNT.

Investigation on electrical parameters between single and double material gate nanoribbon FETs including trap distributions

The presence of multiple interface of gate-oxide and semiconductor in Nano-ribbon FET (NR-FET) causes several defects and leads to the degraded electrical parameters. In this regard, the electrical parameters in the existence of interface trap charges (ITCs) for single material gate (SMG) and double material gate (DMG) NR-FETs are extracted using Technology Computer Aided Design (TCAD) simulator. The effect of Uniform/Gaussian ITCs at the oxide and semiconductor interface on drain current, electrostatic potential, ON current, OFF current, and threshold voltage are reported for these devices. The RF/analog performance like transconductance (gm), gate capacitance (Cgg), and cut-off frequency (fc) are reported for these structures in presence of non-ideal trap distributions. Moreover, the linearity parameters like higher order harmonics in gm (gm2 and gm3), voltage intercept points (VIP2 and VIP3), input intercept power (IIP3), and intermodulation distortion (IMD3) are highlighted for these structures. It is seen that DC, RF/analog, and linearity performance of both the NRFETs are significantly affected by Uniform and Gaussian distribution of ITCs. However, the electrical parameters in DMG NRFET is more immune to ITCs than SMG NRFET. Moreover, both the devices have ON state current in the order of 10−3 A, fc of order THz, and improved linearity behaviour in the presence of ITCs, which indicates sustainability of these devices including ITCs.

Efficient Modulation Recognition by Predictive Correction and Double GRUs via a Lightweight Framework

Automatic modulation recognition (AMR) provides excellent performance advantages over conventional algorithms and plays a key role in modern communication. However, a general challenge is that the channel errors greatly deteriorate the classification capability, and the computational complexity is extremely high. To reduce the offset error of the signal and ensure fewer parameters to save training resources, we demonstrated an efficient modulation recognition scheme combined predictive correction with double Gate Recurrent Unit (GRU), thus realizing a lightweight neural framework. Predictive correction reduces channel errors, and double GRUs are better at capturing long-term dependencies. The results show that when the signal-to-noise ratio is around 18 dB, the highest recognition accuracy can be achieved, and the computational complexity is significantly reduced. The proposed scheme exhibits a tradeoff between the accuracy and the computational complexity, providing an attractive method for modulation recognition.

Synergistic Engineering of Top Gate Stack for Low Hysteresis 2D MoS2 Transistors

Abstract2D semiconductors have emerged as candidates for next‐generation electronics. However, previously reported 2D transistors which typically employ the gate‐first process to fabricate a back‐gate (BG) configuration while neglecting the thorough impact on the dielectric capping layer, are severely constrained in large‐scale manufacturing and compatibility with complementary metal–oxide–semiconductor (CMOS) technology. In this study, dual‐gate (DG) field‐effect transistors have been realized based on wafer‐scale monolayer MoS2 and the gate‐last processing, which avoids the transfer process and utilizes an optimized top‐gate (TG) dielectric stack, rendering it highly compatible with CMOS technology. Subsequently, the physical mechanism of TG dielectric deposition and the corresponding controllable threshold voltage (VTH) shift is investigated. Then the fabricated TG‐devices with a large on/off ratio up to 1.7 × 109, negligible hysteresis (≈14 mV), and favorable stability. Additionally, encapsulated TG structured photodetectors have been demonstrated which exhibit photo responsivity (R) up to 9.39 × 103 A W−1 and detectivity (D*) ≈2.13 × 1013 Jones. The result paves the way for future CMOS‐compatible integration of 2D semiconductors for complex multifunctional IC applications.

Trench Dual Gate Junctionless Field Effect Transistor

Diversified biomolecules sensing is turning out to be the most promising area of research due to ever decreasing healthy lifestyle. Field effect transistorized biosensing approach puts its signature as label free, portable and also very careful pathway. In this present work a trench structured dielectric modulated double gate junction-less field effect transistor (TG-DMJLFET) is urbanized using SILVACO ATLAS simulator for label free detection of biomolecules. The developed structure has two vertically positioned gates in distinct trenches. For immobilizing biomolecules, two cavities are formed in the gate oxide region for dielectric modulation. The dielectric constant (k) has been varied over a wide range of 1.54 (Uricase) to 12(Gelatin) signifying the sensing of diverse charged biomolecules. The sensitivity is evaluated in terms of threshold voltage shift and transconductance . The in-depth electrostatic analysis is illustrated in terms of central potential ,energy band diagram ,drive current and also by the depiction of the electric field .In case of charged biomolecules, the shift in threshold voltage is obtained as 350 mV for change in the di-electric constant (k) ranging from 1.54 to 12. The transconductance alteration is observed as 1.94×10-5 when the k is changed from 3.46 to 12 .The device has showed excellent performance in biomolecules sensing.