Impact of on-chip gate voltage on the electric properties of NbTiN superconducting nanowire transistor

Abstract

In this work, the gate modulation characteristics of superconducting nanowire transistors (SNTs) were investigated under different on-chip gate voltage configurations. By fabricating NbTiN-SNTs with symmetric side gate, we studied the critical current suppression of SNTs under single, opposite, and double voltage gate. We figure out that the gate voltage and leakage current can be adjusted by the gate configuration. Moreover, it revealed an approximately twofold increase in modulation voltage for the opposite gate configuration as compared to the single gate configuration, implying a possible electric field tuned superconductivity. When simultaneously apply voltage on both gates, the onset and offset voltages kept unchanged, but the leakage current is then two times higher than that of single gate. In addition, under all these three types of gate configuration, the suppression of superconductivity coincided with the onset of leakage current, suggesting a potential charge injection mechanism. Our findings demonstrate that both the electric field and charge injection play important roles on the suppression of superconductivity in SNTs, which also contributes to the further optimization and applications of SNT.