Abstract

The interfacial and electrical properties of the multilayer TiON/TaON/InGaAs and TaON/TiON/InGaAs metal-oxide-semiconductor (MOS) capacitors fabricated by alternately RF-sputtering method are investigated and compared. Experimental results show that the former exhibits lower interface-state density, smaller gate leakage current, larger equivalent dielectric constant and higher device reliability than the latter. This is attributed to the fact that the ultrathin TaON interlayer formed on sulfur-passivated InGaAs can effectively reduce the density of defective states and unpin the Femi level at the TaON/InGaAs interface, thus greatly improving the interfacial and electrical properties of the device. Introduction InGaAs has been extensively investigated as alternative channel materials for next-generation nanoscale complementary metal-oxide-semiconductor (CMOS) device applications due to its intrinsic higher electron mobility than that of Si [1]. However, direct deposition of high-k dielectric on InGaAs yields poor electrical characteristics due to easy formation of native oxide on the InGaAs surface. So, the use of different interfacial passivation layer (IPL) prior to high-k deposition on InGaAs has been aggressively studied, achieving the improved interface quality and electrical properties of the device [2-4]. However, the device performance improvement comes at the expense of added processing time, scaling limitation, and complex IPL. To obtain a high-quality interface while negating an IPL, the multiple layers of alternate TaON and TiON are deposited on InGaAs by RF-suputtering Ti and Ta targets, and the interfacial and electrical properties of the prepared MOS capacitors with multilayer TiON/TaON or TaON/TiON as gate dielectric are investigated. As a result, excellent electrical properties are achieved with small gate leakage current, low interface-state density and high device reliability for the multilayer TiON/TaON/InGaAs MOS device. Experimental InGaAs MOS capacitors were fabricated on Si-doped n-In0.53Ga0.47As/n-InP substrate. The wafers were degreased using acetone, ethanol and isopropanol, and cleaned in diluted HF solution, followed by dipping in (NH4)2S solution for sulfur passivation of the InGaAs surface and then dried by N2. Subsequently, a high-k composite gate dielectric (~5 nm) composed of alternate TiN/TaN or TaN/TiN (~0.5 nm per layer) was deposited by RF-sputtering Ti or Ta target in Ar/N2 ambient. A post-deposition annealing (PDA) was performed at 600°C for 60 s in N2 (500 sccm) + O2 (50 sccm) to convert the TaN or TiN alternate layers into TaON or TiON to form two kinds of InGaAs MOS devices (denoted as TiON/TaON/InGaAs and TaON/TiON/InGaAs samples). Finally, Al was thermally evaporated and patterned as gate electrode and also as back electrode, followed by forming gas annealing at 300°C for 20 minutes to reduce their contact resistance. International Conference on Materials, Environmental and Biological Engineering (MEBE 2015) © 2015. The authors Published by Atlantis Press 324 High-frequency (HF, 1-MHz) capacitance-voltage (C-V) and gate leakage current density vs. gate voltage (Jg-Vg) curves of the samples were measured using HP4284A precision LCR meter and HP4156A semiconductor parameter analyzer, respectively. All electrical tests were performed under a lighttight and electrically-shielded condition. Results and discussion Fig. 1 HF (1-MHz) C-V curve for the TiON/TaON/InGaAs and TaON/TiON/InGaAs samples. Fig.1 shows the typical HF (1-MHz) C-V curves of the two samples. It can obviously be seen that the accumulation capacitance drops for the TaON/TiON/InGaAs sample under high positive gate voltages due to the large leakage current, which probably comes from a high density of defective states at the TiON/InGaAs interface [5-6]. However, for the TiON/TaON/InGaAs sample, the accumulation capacitance exhibits a quasi-saturation as the positive gate voltage increases, which should be ascribed to the improved interfacial properties due to suppressed growth of low-k interfacial layer (In/Ga/As oxides) at the InGaAs surface by the ultrathin TaON IPL formed on InGaAs. The interface-state density (Dit) at midgap extracted from the 1-MHz C-V curve is ~1.0× 10 cmeV for the TiON/TaON/InGaAs sample by using the Terman’s method, which is lower than that for the TaON/TiON/InGaAs sample (~7.1×10 cmeV). A smaller negative shift of the flatband voltage (Vfb) for the TiON/TaON/InGaAs sample (-0.32 V) than the TaON/TiON/InGaAs sample (-0.44 V) in Fig. 1 shows a reduced positive equivalent oxide-charge density (Qox) (4.9×10 cm vs. 4.0×10 cm) associated with the interface and near-interface traps. The equivalent k value of gate dielectric is calculated to be 19.8 and 19.6 for the TiON/TaON/InGaAs and TaON/TiON/InGaAs samples, respectively. A slightly larger equivalent k value is achieved for the former than the latter, due to suppressed oxygen diffusion from the high-k gate dielectric to the InGaAs surface by the TaON interlayer and thus less formation of the low-k interfacial oxide. The gate leakage properties of the two samples are shown in Fig. 2. Large gate leakage current density is observed for the TaON/TiON/InGaAs sample. However, for the TiON/TaON/InGaAs sample, the leakage current density is greatly reduced. The smaller gate leakage current of the latter is closely related to its smaller Qox and Dit. In addition, a high-field stress at 3 MV/cm [= (Vg-Vfb)/Tox] for 3000 s is used to examine the reliability of the samples. The Jg-Vg properties are measured before and after the stressing, as shown in Fig. 3. On one hand, the increased gate leakage current after the stress for the two samples could come from carrier charging at the original traps of the oxide layer; and on the other hand, could come from the trap-assisted tunneling of electrons via newly-created interface and near-interface traps [7-8], as shown in Fig. 4. Obviously, the post-stressing increase of the leakage current is smaller for the TiON/TaON/InGaAs sample than the TaON/TiON/InGaAs

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