Multi-die Package Research Articles

The Daniel H. Wagner Prize for Excellence in the Practice of Advanced Analytics and Operations Research: Introduction to the 2023 Competition and Some History on the Prize’s 25th Anniversary

The judges for the 2023 competition selected the three finalist papers featured in this special issue of the INFORMS Journal on Applied Analytics (IJAA). The prestigious Wagner Prize—awarded for achievement in implemented operations research, management science, and advanced analytics—emphasizes the quality and originality of mathematical models along with clarity of written and oral exposition. This year’s winning submission describes the design and deployment of an approach to accommodate the assembly of semiconductor products using multidie packages, a powerful and innovative approach to manufacturing a wide range of strategically designed semiconductors. The authors refer to the problem as the sort-assemble-blend routing problem (SABR-P), and their approach to solving the SABR-P is a combination of genetic algorithms, Monte Carlo simulations, linear programming, and machine learning. The remaining papers describe an integrated approach to system-wide deployment of nurses that facilitates the movement of nurses between hospitals, and a multiple-stage process that consolidates parcels ordered by the same consumer from one or more merchants during the fulfillment process. In addition, we provide some historical perspective on the Daniel H. Wagner Prize for Excellence in the Practice of Advanced Analytics and Operations Research. We show the titles, abstracts, and names and affiliations for its recipients for each year in which the prize has been awarded. Finally, we provide links to the winning papers, which have been published by INFORMS Journal on Applied Analytics (formerly Interfaces). Supplemental Material: Full presentation videos with slides are available in the INFORMS Video Library at https://www.informs.org/Resource-Center/Video-Library and as electronic companions to the INFORMS Journal on Applied Analytics articles.

Squaring Off with M-Series Fan-Out Technology

Currently running at volumes in the millions of units per day on 300mm round format, Deca’s M-Series™ fan-out PLP technology and Adaptive Patterning® are being scaled up at ASE to 600 mm for production. The SEMI standard 600 mm square format pioneered by Deca, provides a 500% increase in usable area per panel providing cost-effective capacity growth as well as a powerful platform for high density integration of multi-die and chiplets in 2D, 2.5D and 3D structures. Deca’s patented Adaptive Patterning® coupled with chip attach compensation modeling overcomes the yield challenges associated with scaling to 600 mm and mitigates the compounding risk associated with the growing number of dies in a package, which is of particular importance for chiplet designs. The use of Laser Direct Imaging (LDI) overcomes the need for reticle stitching and eliminates this barrier for large package body sizes. In addition, 600mm allows for higher efficiency in terms of package count per format area over 300mm round, leading to less waste, thus a lower cost and a more environmentally friendly process. Recent advancements in LDI have allowed the potential to scale the technology to ultra-high density 2µm line & space redistribution layers (RDL) and 5μm vias. Advancement in Adaptive Patterning have led to multi-die packaging solutions without the need for complicated embedded bridge chips. With these ultra-high-density tools at hand, a breakthrough in device interface pitch of 20µm area array for leading edge silicon nodes will be outlined.

Enabling Co-Design of 3D Heterogeneous Packages

The days of ‘throwing it over the wall’ are over. Heterogeneous Integration (HI) is ushering in a new era of electronic product design with collaboration at its core – one that lives or dies on seamless interaction between analog/digital IC teams and package design teams. The use of advanced packaging technologies to combine smaller, discrete chiplets into one system-in-package (SiP) not only pushes the need for more advanced multi-die packaging, it makes packaging part and parcel of the process. And in doing so, it significantly reduces dependance on Moore’s Law at a time in which building an advanced monolithic system-on-chip (SoC) has become prohibitively expensive. For many tech companies, Moore’s Law no longer represents the best technical nor economical path to designing a product. And for a great many of those companies, HI presents a solution – SiPs close to the SoC form factor but with far lower overall cost, greater yield and perhaps most importantly, faster time to market. While SiP as a packaging concept has been around for decades, the recent tsunami of designs that have adopted HI is truly a disruptive change. This presentation will outline some potential solutions to the challenges design teams face when pivoting from monolithic IC design to 3D heterogenous package design.

Advanced Test Technologies for Heterogeneous & 2.5D/3D Packaging

Automotive, AI/ML and 5G markets are demanding increasing levels of integration with respect to memory and compute density. To meet the demand for high-performance products in mission-critical, high-bandwidth applications, the semiconductor industry must look for innovative technologies to continue scaling beyond the silicon manufacturing processes. This is often referred to as “More than Moore”, and one of the most promising methods is heterogenous integration of multiple dies inside the same package (System in Package, or SiP). These dies are typically referred to as chiplets and their interfaces are optimized to operate within a multi-die package for both power, drive strength, interface mechanics and ESD protection. Heterogeneous packages at manufacturing test are faced with quality and reliability challenges due to the accessibility and visibility of traditional test approaches. Dies are assembled over the silicon interposer using very small micro-bumps which may suffer from latent defects such as voids or cracks, potentially posing a reliability risk to the assembled product. On organic substrates, rare resistive shorts, known as bridging shorts, can cause signal integrity and performance degradation. These types of latent defects, although rare, could cause a system failure over time if not screened out during final test or detected during in-field operation. To address these challenges, proteanTecs and Advantest have deployed a joint solution at manufacturing test. proteanTecs provides a monitoring solution for heterogeneous packaging based on chip telemetry, combining deep data with machine learning algorithms. proteanTecs’ patent-protected solution is comprised of small-footprint, digital-only agents for monitoring the performance of the parallel interface. These agents (monitoring IP) are designed for analytics. The fact that they have a small footprint, allows them to be placed next to each pin inside the parallel die-to-die (D2D) PHY, to achieve 100% coverage and with no impact on the signal behavior, quality, or timing. proteanTecs’ data analytics platform then trains models that are deployed at test or in the field. To achieve the highest levels of performance, proteanTecs has partnered with Advantest on the ACS Edge™ for real-time decision-making. ACS Edge™ is a high-performance, highly secure edge compute and analytics solution that enables ultra-fast algorithmic AI decision-making with millisecond latencies during test execution. It connects to the user’s test equipment via a private, high-speed encrypted link and uses the advanced container hub to run the user’s protected applications while protecting and keeping secure the user’s data and analytics. Another key piece of the ACS ecosystem is the ACS Solution Store which provides ease of access to ACS real-time data infrastructure solutions. In this paper, we will provide details for the integrated solution and silicon results. We will highlight how the solution provides new levels of visibility for real-time adaptive testing.

Applying IEEE Test Standards to Multidie Designs

<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Editor’s notes:</i> The ”chiplet” components that, after stacking, constitute a multidie package, can be complex system-on-chips in their own right. Consequently, IEEE Std 1838, the recently released standard for test access in 3-D die stacks, potentially interacts with many other Design-for- Test (DfT) standards, which all might have been used in these chiplets. This article provides a guided tour through the growing set of IEEE DfT standards in the context of an IEEE 1838-compliant design. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">—Erik Jan Marinissen, imec</i>

Guest Editors’ Introduction: Special Issue on Design and Test of Multidie Packages

<bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">In 2017, <i>IEEE Design&amp;Test</i></b> published a special issue on “3D-TEST” (referring to both the workshop with that name, as well as the topic), featuring three articles on various test-related issues of the AMD Radeon R9 Fury, a marvel of multidimensional packaging. Since then, the market has lurched tentatively in the same direction. Expectations were high for single-tower many-die stacks, but the realities of power and thermal issues still hold that promise at bay. Slowly, the market has been tackling each obstacle placed in front of it. Once thought to be a mere stepping-stone to true 3D-IC stacking, side-by-side stacking onto an interposer has created its own place on the product roadmaps and is here to stay. The word “chiplet” has yet to claim space in the dictionary, but chiplets (dies meant to be stacked as part of a larger chip) are front and center in advanced chip design projects. Placed upon passive or active interposers, these building blocks enable the path to heterogeneous integration: architecting submodules of a package with various technology nodes, and therefore with just the right balance of performance and cost. The debate has shifted to interchiplet communications. HBI+ and OpenHBI, ultra-short reach(USR)/extra-short reach (XSR), and the nascent Universal Chiplet Interconnect Express (UCIe) interface are battling for the structured high-speed interconnect market. Certainly, memory stacking has won with high bandwidth memory (HBM) stacks seen on several production devices.

Special Issue on Design and Test of Multidie Packages

<fig orientation="portrait" position="float" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <graphic orientation="portrait" position="float" xlink:href="pande-3193629.tif"/> </fig> <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">The articles in</b> this issue are divided into two groups: 1) the first group belongs to the Special Issue on Design and Test of Multidie Packages and 2) the second group consists of the general interest articles.

Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems

This paper presents the integration of resonant clocking to multi-die architectures to synchronize individual chiplets connected through an active silicon interposer. The proposed inter-chiplet synchronization through the active silicon interposer rotary oscillator array (ASI-ROA) provides a unitary clock domain to the multiple die (i.e. multiple chiplets) in the package with a very low design overhead. System performance analysis is performed with parasitics-extracted, post-layout simulation models of two different sizes of representative heterogeneous multi-die architectures, each with varying number of RISC-V cores per die. Each RISC-V core of the multi-die package belongs to the unitary clock domain, designed with ASI-ROA to operate at a frequency of 2 GHz. The proposed architecture is investigated for robustness in frequency and skew across the multi-die system (MDS) with SPICE based simulations of post layout models, demonstrating variations of only 80 MHz for a 2 GHz target frequency. The power savings are upto 41% for the overall MDS, compared to an equivalent implementation with a contemporary ADPLL used to synchronize the multiple chiplets over the active interposer. The average clock skew of the completely resonant architecture presented in this work is 8.2 ps.

Specialized Wirebond Process Configuration on Advanced Multi-Die Package

Wirebonding process is one important assembly process responsible for providing electrical connections between the silicon die and the external leads of a semiconductor package or device. The process also brings along some challenges as the device becomes more complex and critical. This paper is focused on the prevention of the broken wire on neck during wirebonding process of an advanced semiconductor package with multi-die configuration. Extensive wire loop character-ization and optimization was done and a specialized wirebonding configuration solution was formulated. Ultimately, the solution prevented high loop and wire sagging that could touch or short-circuit the silicon die. For future works, the configuration could be applied on packages with comparable construction.

Deep ultraviolet excimer laser processing for the micro via hole on semiconductor package

Moore's law has almost reached the limit of resolution on semiconductor die and, therefore, multidie packaging is one of the alternative solutions. Substrate materials currently use organic build-up films and silicon substrates [through silicon via (TSV)] in applications. But recently, organic films, too, have reached the resolution limit, and TSV is expensive. In this situation, nonalkali glass (glass) and fused silica (SiO2) substrates are expected to be good alternatives in high-frequency signal transfer applications like 5G telecommunication. But the via holes are hard to process with less defects (tips and cracks) on the glass and SiO2 substrates. Deep ultraviolet (DUV) excimer laser ablation is expected to have a finer (&amp;lt;10 μm) resolution with a shorter wavelength (248–193 nm) and also hard material processing with a higher photon energy (5–6.4 eV). Therefore, the authors have explored the application of the DUV excimer laser ablation process for a via hole on hard materials like glass and SiO2 substrates. In this study, they have investigated the via hole quality through the DUV excimer laser ablation process. The results show the possibilities of micromachining on both glass and SiO2 substrates. The authors have succeeded by achieving a value of &amp;lt;50 μm through the via hole grid aspect ratio of 6 on the glass substrate without any significant defects. As the ablation rate is quite an affordable value, DUV excimer lasers are expected to play a crucial role in the next-generation manufacturing process for semiconductor packages. The authors also investigate the SiO2 substrate with DUV excimer lasers.

Packaging Renaissance with Chiplets

Abstract With ever shrinking advanced CMOS nodes and evolution of systems with increasing complexity, the traditional SoC paradigm is facing extensive challenges in terms of yields and heterogeneity. The emerging industry solution to this has been to partition the SoCs into smaller units, with each unit performing a certain (though exclusive) function. This drove the birth of “chiplets”. With advent of chiplets, the traditional function of packaging as an after-thought to chip development has got a revolutionary face-lift. Packaging is now enabling interconnects to replace on-chip global interconnects. The onus now is on packaging to get the chiplets to integrate and communicate with each other such that the net performance is equivalent to or better than SoC. This has spawned a renaissance in field of semiconductor packaging, with newer multi-die packaging technologies being productized to realize newer and better interconnects. Some examples of these emerging technologies include advanced flip-chip, 2.5D, 2.1D, 3D, Wafer Level Fan-Out, and Bridge Technologies. AMD is at forefront of chiplet technologies, with extensive 7nm chiplet based product portfolio catering to the HPC market. This talk will discuss the current state of chiplet packaging technologies.

The bifurcation of advanced packaging

Following a similar trend from the 1990's, IC package design is experiencing a sea change. As a refresher, the 1990's is when the ball grid array (BGA) came along, introducing a whole new set of design tool requirements. The mechanical design tools used for the previous generation of lead frame styled packages were no longer capable of supporting the new design requirements of the BGA. In short, the BGA introduced multi-layer routable organic and ceramic substrates and new possibilities for stacking (and embedding) multi-die, requiring designers to abandon their mechanical design tools and look at new solutions for doing package design. On top of that, IO's were switching faster than ever, requiring engineers to look at new ways of electrically characterizing these designs. As a result, a couple of EDA companies stepped up and adapted their printed circuit board (PCB) layout and analysis tools for that generation of BGA-based advanced packaging. Problem (more or less) solved! Fast forward to today and we see a very similar trend. Now being introduced at a rapid pace, are new advanced IC packaging solutions that have a lot more silicon content, wafer stacking and, in some cases, chips being packaged directly at the wafer-level at traditional IC foundries, skipping the traditional OSAT model of the past. Make no mistake, this is a significant change to the status quo of BGA package design tools of the past. The PCB-like flows that were established for BGA design are likely not the path forward for technologies like, 2.5D/3D IC and fan-out wafer-level packaging (FOWLP). Instead, in all likelihood IC design tools and flows will need to be slightly adapted to support the next generation of package designs. Let's start with foundry-based FOWLP. In this case, induvial dice are placed on a chip-carrier with additional spacing between them. Molding is poured in the empty space and then an array of bumps (UBM) and the connectivity (RDL) are added. In foundry-based flows, these UBM and RDL layers require IC-styled routing/metal fill and mask generation from the layout tool. In addition, these masks must be verified with traditional IC DRC/LVS tools. It's clear that some kind of hybrid advanced packaging flow using some traditional IC tools in the flow is required to support this type of design. And in fact, if you look at the largest semiconductor foundries reference flow tools, you will find this to be true. This presentation further examines the design tool/flow requirement for FOWLP, 2.5D/3D IC and future multi-die packaging technologies.

Innovative Integration Solutions for SiP Packages Using Fan-Out Wafer Level eWLB Technology

Abstract Fan-Out Wafer Level Packaging (FOWLP) has been established as one of the most versatile packaging technologies in the recent past and already accounts for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduced overall form factor as well as cost effectiveness. The increasing complexities in achieving a higher degree of performance, bandwidth and better power efficiency in various markets are pushing the boundaries of emerging packaging technologies to smaller form factor packaging designs with finer line/width spacing as well as improved thermal/electrical performance and the integration of System-in-Package (SiP) or 3D capabilities. SiP technology has been evolving through utilization of various package technology building blocks to serve the market needs with respect to miniaturization, higher integration, and smaller form factor as cited above, with the added benefits of lower cost and faster time to market as compared to silicon (Si) level integration, which is commonly called system-on-chip or SoC. As such, SiP incorporates flip chip (FC), wire bond (WB), and fan-out wafer-level packaging (FOWLP) as its technology building blocks and serves various end applications ranging from radio frequency (RF), power amplifiers (PA), Micro-Electro-Mechanical-Systems (MEMS) and Sensors, and connectivity, to more advanced application processors (AP), and other logic devices such as graphics processing units (GPUs)/central processing units (CPUs). FOWLP, also referred to as advanced embedded Wafer Level Ball Grid Array (eWLB) technology, provides a versatile platform for the semiconductor industry's technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D SiP configurations. This paper presents developments in SiP applications with eWLB/Fan-out WLP technology, integration of various functional blocks such as wire bonding, Package-on-Package (PoP), 2.5D, 3D, smaller form factor, embedded passives, multiple redistribution layer routing and z-height reduction. Test vehicles have been designed and fabricated to demonstrate and characterize these low profile and integrated packaging solutions for mobile products including Internet of Things (IoT)/wearable electronics (WE), MEMS and sensors. Finer line/width spacing of 2/2mm with multiple redistribution layers (RDL) are fabricated and implemented on the eWLB platform to enable higher interconnect density and signal routing. Assembly process details, component level reliability, board level reliability and characterization results for eWLB SiP will be discussed.

Thermal Evaluation of 2.5-D Integration Using Bridge-Chip Technology: Challenges and Opportunities

In this paper, 2.5-D integrated circuits (ICs) using bridge-chip technology are thermally evaluated to investigate thermal challenges and opportunities for such multi-die packages. To this end, the objectives of this paper are twofold. First, thermal benchmarking of a number of 2.5-D integration approaches is performed and compared to 3-D ICs for completeness. Thermal modeling shows that the evaluated 2.5-D integration approaches exhibit similar thermal characteristics, but show significant improvements compared to 3-D IC solutions with the same power consumption. Second, this paper explores bridge-chip-based 2.5-D integrated systems as a function of bridge-chip thickness, thermal interface material properties, microbump properties, die thickness, die thickness mismatch, and die-to-die spacing along with transient analysis to investigate time-domain thermal coupling. Results suggest that a die thickness mismatch of 100 $\mu \text{m}$ can increase the maximum temperature by 25.8% Therefore, the die thickness mismatch should be kept as small as possible, and the hottest die should be the thickest. Moreover, reducing die-to-die space from 1 to 0 mm increases thermal coupling, and the low-power dice, such as DRAM, can have a temperature increase of 6.1%.

(Invited) VLSI-CMOS Device Technology Scaling Landscape Based on Fully-Depleted SOI and 3D-FinFET Technologies for the Internet of Everything Era

System- and process-level innovations based on VLSI-CMOS technologies are the drivers to continue Moore’s Law. Especially in the last decade an ever-increasing component integration on SoC’s has driven cost scaling and will continue to do so while approaching the IoT and wearable device area. To keep pace with the manufacturing cost per device scaling an acceleration of new processing methods, concepts and materials has been introduced, such as local strained Si, high-k metal gate, ultra-low-k, 3D FinFET and FDSOI devices. New integration techniques like double and quadruple patterning are needed since EUV lithography cannot be easy introduced in high volume manufacturing. The inflection on the cost per gate trend can be intercepted by differentiated technologies that serve markets for the respective applications such as 22nm and 12nm FDSOI. Those technologies offer a wide variety and individualism for designs to serve the IoT/E era perfectly. SoC innovations need to focus on 3D multi-die package integrations on system level.

(Invited) VLSI-CMOS Device Technology Scaling Landscape Based on Fully-Depleted SOI and 3D-FinFET Technologies for the Internet of Everything Era

Smart and innovative products are using the convergence of ubiquitous sensing and the communication by the internet. The so called Internet of Things/Everything (IoT/IoE) emerges from the traditional computing and mobile market and impacts every era in humans’ lives. Moore’s Law is the driver of these innovations in increasing component integration on SoC’s to deliver the right combination of performance, power, and cost to match the appropriated application. To continue to create compelling products, it will increasingly require all advancements and differentiations, more directly linking the CMOS-VLSI scaling to the integrated circuits; in an era where future systems may be different than the computers we are familiar with. A large variety of emerged technology concepts especially in the communication and sensor area as well as non-volatile memories will converge with the well-established VLSI-CMOS technology. The main requirements on the single semiconductor device and technologies are lowest leakage at lowest voltage operation at the minimum cost. Differentiated technologies such as 22nm and 12nm Fully Depleted Silicon on Insulator (FDSOI), common partially depleted SOI (PDSOI) RF as well as novel non-volatile memory concepts are entering the markets. Furthermore, SoC innovations will focus on 3D multi-die package integrations on system level to growth technologies into the Internet of Everything area. Planar CMOS devices especially in 28nm and 20nm are currently the mostly used technologies for mass production microprocessors and SoC’s since it’s at an optimized spot of cost and performance. Over the last decades new processing techniques as well as new materials have been introduced such as strained Si, high-k metal gate and ultra-low-k. With the non-manufacturable arrival of EUV lithography integration techniques such as double and quadruple patterning, self aligned contacts; air-gap interconnects as well as new materials are needed for VLSI technologies of 7nm and beyond. 3D FinFET devices as well as new device architectures are required to continue an over-scaling in order to maintain the historical Moore’s Law to overcome the increased cost per gate. Simultaneously, the effort on variation reduction, performance and yield improvements increases exponentially for the design and manufacturing community. To keep pace with the technology over-scaling advanced techniques and solutions on the design and process integration as well as manufacturing processes are necessary. Reducing all parasitic resistances and capacitances is key for technologies below 7nm to gain in further SoC scaling while maintaining its performance level. The inflection on the cost per gate trend can be intercepted by differentiated technologies that serve markets for the respective applications such as 22nm and 12nm FDSOI. Those technologies offer a wide variety and individualism for designs to serve the IoT/E era perfectly. The FDSOI technology is a real independent multi-gate technology which can span an infinite VTH space for any circuit design. In addition it’s well suited for low and lowest power applications as well as RF, mmWave, analog and mixed Signal SOC’s. Since it’s a planer technology, process and technology elements from previous nodes can be transformed into this novel architecture. With its diffusion less concept scaling is possible down to the 12nm technology node while maintaining the lowest cost trend by saving up to 30% fewer mask steps. The performance produces NFET (PFET) drive currents of up to 910μA/µm (856μA/µm) at 0.8V and 100nA/µm IOFF. For ultra-low power applications, it offers low-voltage operation down to 0.4V Vmin. Ultra-low leakage devices serve up to 1pA/µm IOFF and body-biasing can be used to actively trade-off power and performance. RF/Analog characteristics are achieved including high fT/fMAX of 375GHz/290GHz and 260GHz/250GHz for NFET and PFET, respectively. The high fMAX extends the capabilities to 5G and mmWave (>24GHz) RF applications. Implementing an increased amount of sub-systems like graphic, video, TV, RF applications, sensor interfaces etc. challenges occur on I/O interface components and sub-system scaling. What once was 5-15% of a SoC die area is rapidly increased to 30-40% as the digital side over-scales in attempt to keep costs in line with Moore’s law. New 3D IC stacking technology concepts being introduced, which need to maintain the over-scaling and keeping the overall cost scaling on Moore’s Law historical trend line. Cost scaling can be enhanced with advanced methods on direct wafer boding, 3D-TSV or inductive coupling, which will come at a total power tradeoff, as the total combined die area will increase compared to a monolithic die. Continues innovation in area over-scaling and derivative technology approaches such as FDSOI will keep the current SoC’s scaling near the historic Moore’s Law trend to serve appropriate applications optimized in performance, power, and cost.

Creating Semiconductor Value through Advanced Package Technology

Over the past few years, there has been a significant shift from PCs and notebooks to smartphones and tablets as drivers of advanced packaging innovation. In fact, the overall packaging industry is doing quite well today as a result, with solid growth expected to create a market value in excess of $30B USD by 2020. This is largely due to the technology innovation in the semiconductor industry continuing to march forward at an incredible pace, with silicon advancements in new node technologies continuing on one end of the spectrum and innovative packaging solutions coming forward on the other in a complementary fashion. The pace of innovation has quickened as has the investments required to bring such technologies to production. At the packaging level, the investments required to support the advancements in silicon miniaturization and heterogeneous integration have now reached well beyond $500M USD per year. Why has the investment to support technology innovation in the packaging community grown so much? One needs to look no further than the complexity of the most advanced package technologies being used today and coming into production over the next year. Advanced packaging technologies have increased in complexity over the years, transitioning from single to multi-die packaging, enabled by 3-dimensional integration, system-in-package (SiP), wafer-level packaging (WLP), 2.5D/3D technologies and creative approached to embedding die. These new innovative packaging technologies enable more functionality and offer higher levels of integration within the same package footprint, or even more so, in an intensely reduced footprint. In an industry segment that has grown accustomed to a multitude of package options, technology consolidation seems evident, producing “The Big Five” advanced packaging platforms. These include low-cost flip chip, wafer-level chip-scale package (WLCSP), microelectromechanical systems (MEMS), laminate-based advanced system-in-package (SiP) and wafer-based advanced SiP designs. This presentation will address ‘The Big Five’ packaging platforms and how they are adding value to the Semiconductor Industry.

Thermal analysis, design, and characterization of a reconfigurable switch matrix based on LTCC technology for satellite communications

The thermal characteristics of a reconfigurable switch matrix (RSM) module based on low temperature co-fired ceramic (LTCC) technology are presented. Owing to the PIN-diodes based design, a static power of 1.6 W is dissipated on the ceramic package; the double-sided mounting and integrated bias circuitry demands determination of the temperature distribution within the module. A finite-element thermal simulation model was validated by an infrared (IR) thermograph; the steady-state temperature distribution on the surface of the package estimated by the simulation model differs to the IR measurements by &amp;lt; 1%. This temperature distribution is the result of the thermal interaction among components on the multi-die package with different electrical power dissipation. The temperature on the multi-throw switch monolithic microwave integrated circuit (MMIC) is elevated by ~36.7 K relative to the ambient temperature. The peak temperature occurs on the current-limiting resistors in the bias circuitry; the peak temperature is estimated to be ~45 K above the ambient. In a later version of the RSM, the bias current was reduced by 50%, current-limiting resistor was replaced by two parallel resistors, and additional thermal vias and conductive pads were introduced on the ceramic package. The cumulative effect is a temperature distribution on the package with lowered values. Compared to its predecessor, the temperatures at the current-limiting resistor and the MMIC are reduced by ~20 K and ~14 K, respectively. With one heat source active on the ceramic package at a time, the resulting steady-state temperatures on this source and the remaining heat sources provided an estimate of the self- and transfer-thermal resistances, respectively. The reciprocity of the heat flow on the package and the three-dimensional symmetric layout required only ‘4’ thermal simulations to determine the symmetric thermal resistance matrix. The significantly reduced values of the computed matrix for the later version of the RSM module demonstrated lower thermal resistance to the ambient, compared to its predecessor. Lastly, the results of thermal measurements conducted with a vacuum wafer prober are presented, in order to validate RSM functionality for vacuum pressures (≤ 1 mPa) and temperatures between 248 K and 338 K; the control current and the transmission coefficient demonstrated variations of ≤ 0.5% and −0.015 dB/K, respectively.

Path Finding for Multiple Platforms

With the increasing complexity of today's SOCs and the growth in multi-die packaging, companies are recognizing the value of cross-domain collaboration between the IC, package substrate and PCB design groups. High pin count devices coupled with cost sensitivity drive engineers to reconsider how they plan, optimize and automate the I/O placement on their chips, while targeting multiple packaging variables, which have direct impact on how the PCB will be designed. In some instances, informal design flows based on multiple EDA design tools have been pieced together. This is a step in the right direction; however, without a central repository for the data or accurate device modeling and rule-based optimization, design intent is often misinterpreted or lost and redundancy is often introduced into the flow. This presentation outlines a co-design methodology that allows design teams the ability to easily plan and optimize I/O and connectivity from a chip(s), through multiple packaging variables while targeting multiple different system platforms (PCBs). Using this planning, optimization and design methodology, engineering teams for the IC, the Package and the PCB would drive rule-based I/O level optimization and perform ball-out studies from their respective domains, all while visualizing the impact across the complete system. Key features and advantages of this methodology are:Multi-mode connectivity management for cross-domain pin/signal mapping/shortingUser definable rules for I/O and ball-out assignmentsRobust support for feasibility analysis and rapid prototypingFully automated library developmentDirect integration to multi-mode physical layout toolSeamless interface to 2D and 3D EM analysis enginesTight interface with CFD based thermal analysis solutionEDA vendor neutral flow The result of implementing this methodology will be a chip(s) that is fully optimized for its package(s) and PCB(s). This solution drives down the cost of the package and PCB through layer reduction and tighter control of the design process without impacting the cost of the chip.

Reliability Assessment of Through-Silicon Vias in Multi-Die Stack Packages

A thermo-mechanical reliability study of through-silicon vias (TSVs) is presented in this paper. TSVs are used to interconnect stacked dies to achieve 3-D packages. As the core of the TSV contains high coefficient of thermal expansion (CTE) copper surrounded by low-CTE SiO2 and Si materials, the thermo-mechanical reliability of TSVs is a concern. When dies with such TSVs are stacked and packaged, the presence of additional structures and associated materials could introduce different thermo-mechanical concerns compared with free-standing wafers. This paper presents 3-D finite-element models for studying the thermo-mechanical stresses in TSVs in free-standing wafers and in stacked dies, which are packaged. Warpage measurements have been used to validate the finite-element modeling approach. The results from the finite-element models show that the TSV stresses in a packaging configuration are typically lower than the TSV stresses in a free-standing wafer configuration. In addition, it is seen that the microbumps connecting adjacent dies experience high magnitude of inelastic strain, indicating that such locations are of reliability concern.