Guest Editors’ Introduction: Special Issue on Design and Test of Multidie Packages

Abstract

<bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">In 2017, <i>IEEE Design&amp;Test</i></b> published a special issue on “3D-TEST” (referring to both the workshop with that name, as well as the topic), featuring three articles on various test-related issues of the AMD Radeon R9 Fury, a marvel of multidimensional packaging. Since then, the market has lurched tentatively in the same direction. Expectations were high for single-tower many-die stacks, but the realities of power and thermal issues still hold that promise at bay. Slowly, the market has been tackling each obstacle placed in front of it. Once thought to be a mere stepping-stone to true 3D-IC stacking, side-by-side stacking onto an interposer has created its own place on the product roadmaps and is here to stay. The word “chiplet” has yet to claim space in the dictionary, but chiplets (dies meant to be stacked as part of a larger chip) are front and center in advanced chip design projects. Placed upon passive or active interposers, these building blocks enable the path to heterogeneous integration: architecting submodules of a package with various technology nodes, and therefore with just the right balance of performance and cost. The debate has shifted to interchiplet communications. HBI+ and OpenHBI, ultra-short reach(USR)/extra-short reach (XSR), and the nascent Universal Chiplet Interconnect Express (UCIe) interface are battling for the structured high-speed interconnect market. Certainly, memory stacking has won with high bandwidth memory (HBM) stacks seen on several production devices.