Field-effect Transistor Model Research Articles

Benchmarking contact quality in N-type organic thin film transistors through an improved virtual-source emission-diffusion model

Due to nonideal behavior, current organic thin film transistor technologies lack the proper models for essential characterization and thus suffer from a poorly estimated parameter extraction critical for circuit design and integration. Organic thin film transistors are often plagued by contact resistance, which is often less problematic in inorganic transistors; consequently, common models used for describing inorganic devices do not properly work with organic thin film transistors. In this work, we fabricate poly{[N,N′-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5′-(2,2′-bithiophene)} based organic thin film transistors with reduced contact resistance through the introduction of metallic interlayers between the semiconductor and gold contacts. The addition of 10 nm thick manganese interlayer provides optimal organic thin film transistor device performance with the lowest level of contact resistance. Improved organic thin film transistors were characterized using an improved organic virtual-source emission diffusion model, which provides a simple and effective method to extract the critical device parameters. The organic virtual-source emission diffusion model led to nearly perfect prediction using effective gate voltages and a gate dependant contact resistance, providing a significant improvement over common metal–oxide–semiconductor field-effect transistor models such as the Shichman–Hodges model.

Model and Structure Analysis of a New Tunneling Field Effect Transistor

Model and Structure Analysis of a New Tunneling Field Effect Transistor

Experimental studies and a double gate JFET model for analog integrated circuits

One of directions of improving parameters of analog integrated circuits is a development of new and modernization of existing designs of integrated elements without significantly changing of a technological route of integrated circuit manufacturing with a simultaneous creation of new integrated elements models. The article considers the results of experimental studies of the double gate junction field-effect transistor manufactured according to the 3CBiT technological route of JSC Integral. Based on the obtained results, the electrical model of double gate junction field-effect transistor is proposed, which describes the features of its application in analog integrated circuits. Comparison of I-V characteristics of measurements results and created model simulation are presented. A small capacity and a reverse current of a double gate junction field-effect transistor top gate, an ability to compensate for the DC (direct current) component of an input current provide a significant improvement in the characteristics of analog integrated circuits such as electrometric operational amplifiers and charge-sensitive amplifiers. The developed double gate junction field-effect transistor can be used in signal readout devices required in the analog interfaces of space instrument sensors and nuclear electronics.

An Accurate Drain Current Model of Dual Material Double Gate Metal Oxide Semiconductor Field Effect Transistor

An Accurate Drain Current Model of Dual Material Double Gate Metal Oxide Semiconductor Field Effect Transistor

Thermal performance of diamond field-effect transistors

In this report, the thermal performance of a hydrogen (H)-terminated diamond field-effect transistor (FET) is investigated using Raman spectroscopy and electrothermal device modeling. First, the thermal conductivity (κdiamond) of the active diamond channel was determined by measuring the temperature rise of transmission line measurement structures under various heat flux conditions using nanoparticle-assisted Raman thermometry. Using this approach, κdiamond was estimated to be 1860 W/m K with a 95% confidence interval ranging from 1610 to 2120 W/m K. In conjunction with measured electrical output characteristics, this κ was used as an input parameter for an electrothermal device model of an H-terminated diamond FET. The simulated thermal response showed good agreement with surface temperature measurements acquired using nanoparticle-assisted Raman thermometry. These diamond-based structures were highly efficient at dissipating heat from the active device channel with measured device thermal resistances as low as ∼1 mm K/W. Using the calibrated electrothermal device model, the diamond FET was able to operate at a very high power density of 40 W/mm with a simulated temperature rise of ∼33 K. Finally, the thermal resistance of these lateral diamond FETs was compared to lateral transistor structures based on other ultrawide bandgap materials (Al0.70Ga0.30N, β-Ga2O3) and wide bandgap GaN for benchmarking. These results indicate that the thermal resistance of diamond-based lateral transistors can be up to ∼10× lower than GaN-based devices and ∼50× lower than other UWBG devices.

The Graphene Field Effect Transistor Modeling Based on an Optimized Ambipolar Virtual Source Model for DNA Detection

The graphene-based Field Effect Transistors (GFETs), due to their multi-parameter characteristics, are growing rapidly as an important detection component for the apt detection of disease biomarkers, such as DNA, in clinical diagnostics and biomedical research laboratories. In this paper, the non-equilibrium Green function (NEGF) is used to create a compact model of GFET in the ballistic regime as an important building block for DNA detection sensors. In the proposed method, the self-consistent solutions of two-dimensional Poisson’s equation and NEGF, using the nearest neighbor tight-binding approach on honeycomb lattice structure of graphene, are modeled as an efficient numerical method. Then, the eight parameters of the phenomenological ambipolar virtual source (AVS) circuit model are calibrated by a least-square curve-fitting routine optimization algorithm with NEGF transfer function data. At last, some parameters of AVS that are affected by induced charge and potential of DNA biomolecules are optimized by an experimental dataset. The new compact model response, with an acceptable computational complexity, shows a good agreement with experimental data in reaction with DNA and can effectively be used in the plan and investigation of GFET biosensors.

Design of Low-Power and PVT-Aware Quaternary Adder Circuits Based on Virtual Source-CNTFET Model

Two new robust quaternary half adder (QHA) circuits (one single source and one multiple sources) are proposed in this work for low power applications. The proposed circuits are designed in hybrid fashion based on three types of quaternary inverter circuits and compared with recently proposed existing models in terms of number of supplies, power dissipation, delay, power-delay product (PDP) and transistor count through extensive simulations in Cadence Virtuoso platform using Stanford’s Virtual Source-Carbon Nanotube Field Effect Transistor (VS-CNTFET) model. The sensitivity of the circuits in response to process parameters, voltage and temperature (PVT) variations are also evaluated. The proposed circuit with multiple sources has the lowest values of 4.92 uW for power consumption and 0.124 fJ for PDP compared to all other designs. Simulation results also demonstrate better stability to PVT variation for both the proposed architectures with respect to power and PDP parameters. In order to evaluate the competency of the proposed QHAs, quaternary full adder (QFA) circuits are designed using the proposed QHAs and other relevant models. Extensive simulation data confirm that the proposed circuits outperform others in terms of power penalty.

A dual gate material tunnel field effect transistor model incorporating two‐dimensional Poisson and Schrodinger wave equations

AbstractThis paper presents an accurate analytical model of surface potential and drain current for a long channel dual material gate (DMG) tunneling field‐effect transistor (TFET) with the addition of nonlinear inversion charge developed at the channel/drain interface region, ambipolar characteristic, and quantum confinement. The model includes the effect of dual metal gate work function as it controls the threshold voltage without considering a fully depleted undoped channel region. The current model includes the effect of charge accumulation at the interface of two gates and an appropriate mathematical expression of nonlinear inversion charge developed at the interface of two gates has been derived from the two‐dimensional (2D) Schrodinger wave equation incorporating quantum confinement. The model is effective to capture transfer characteristics at Sub 10 nm body thickness. A high ION/IOFF ratio and less than 27 mV/decade subthreshold swing are achieved at 2 nm body thickness which is desirable for low power VLSI application. The proposed model has been compared and calculated by Sentaurus TCAD with fair accuracy and a good resemblance, including ambipolar characteristics at sub 10 nm body thickness has been achieved.

Impact of thermally -aware environmental conditions on double gate carbon nanotube FET

In this paper, a temperature dependent analytical model of double gate carbon nanotube field effect transistor (DG-CNTFET) has been developed to evaluate the performance of DG-CNTFET under variable thermal environmental conditions. Using the developed model, I–V characteristics of DG-CNTFET have been obtained by nano-TCAD ViDES (nano-Technology Computer Aided Design ViDES) simulator. Further, the effect of temperature on other performance parameters such as output characteristics, ON current, OFF current, subthreshold swing and drain conductance have also been obtained for a temperature ranging from 250 K to 350 K. It has been observed that with increase in temperature, drain current rises which further influence the I–V characteristics of DG-CNTFET. From results, it is revealed that the ON current and drain conductance of DG-CNTFET gets increased with variable temperature. Further, it is also presented in paper that subthreshold swing is also increased under variable thermal environment conditions.

Quantum capacitance transient phenomena in high-k dielectric armchair graphene nanoribbon field-effect transistor model

Graphene Nanoribbons (GNRs) are an emerging candidate to challenge the place of current semiconductor-based technology. In this work, we extend a model for Armchair Graphene Nanoribbons Field-Effect Transistor (AGNRFET) to the high-k dielectrics realm and examine the influences of quantum capacitance on its transient phenomena. The model is coded with Verilog-A and evaluated through SPICE simulations. We have considered a comparison between the extended model with and without the influence of the quantum capacitance. Simulation results show a realistic scenario where influence of the quantum capacitance significantly impacts the transient behaviour in circuit design. This proves the proposed model to be a valuable aid for the circuit design of future graphene-based applications.

TID Circuit Simulation in Nanowire FETs and Nanosheet FETs

In this study, the effects of the total ionizing dose (TID) on a nanowire (NW) field-effect transistor (FET) and a nanosheet (NS) FET were analyzed. The devices have Gate-all-around (GAA) structure that are less affected by TID effects because GAA structures have better gate controllability than previously proposed structures, such as planar MOSFETs and FinFETs. However, even for GAA devices with the same channel cross-sectional area and equivalent oxide thickness, structural differences can exist, which can result in different tolerances of TID effects. To observe the device and circuit operation characteristics of these GAA devices with structural differences, n-type and p-type devices were designed and simulated. The circuit simulation according to TID effects was conducted using Berkeley short-channel insulated-gate FET model (BSIM) common multi-gate (CMG) parameters. The NS-FET generated more VT shift than the NW-FET because the NS-FET had a wider gate oxide area and channel circumference, resulting in more interface hole traps. The abnormal VT shift leads to causing unstable circuit operation and delays. Therefore, it was confirmed that the ability of the NW-FET to tolerate TID effects was better than that of the NS-FET.

Monolayer and bilayer graphene field effect transistor using Verilog-A

Monolayer and bilayer graphene field effect transistor modeling is presented in this paper. The transport model incorporated, works well for both drift diffusive and ballistic conditions. The validity of the model was checked for various device dimensions and bias voltages. Performance parameters affecting operation of graphene field effect transistor in various region of operation are optimized. Model was developed to verify transfer characteristics for monolayer and bilayer graphene field effect transistor. Results obtained prove the ambipolar property in Graphene. MATLAB is used for numerical modeling for systematic performance evaluation of parameters in graphene. The tool used to simulate the characteristics is cadence Verilog-A which describe analog component structure.

Artificial Neural Network-Based Compact Modeling Methodology for Advanced Transistors

The artificial neural network (ANN)-based compact modeling methodology is evaluated in the context of advanced field-effect transistor (FET) modeling for Design-Technology-Cooptimization (DTCO) and pathfinding activities. An ANN model architecture for FETs is introduced, and the results clearly show that by carefully choosing the conversion functions (i.e., from ANN outputs to device terminal currents or charges) and the loss functions for ANN training, ANN models can reproduce the current-voltage and charge-voltage characteristics of advanced FETs with excellent accuracy. A few key techniques are introduced in this work to enhance the capabilities of ANN models (e.g., model retargeting, variability modeling) and to improve ANN training efficiency and SPICE simulation turn-around-time (TAT). A systematical study on the impact of the ANN size on ANN model accuracy and SPICE simulation TAT is conducted, and an automated flow for generating optimum ANN models is proposed. The findings in this work suggest that the ANN-based methodology can be a promising compact modeling solution for advanced DTCO and pathfinding activities.

Hybrid Modeling and Sensitivity Analysis on Reduced Graphene Oxide Field-Effect Transistor

The reduced graphene oxide (RGO) field-effect transistor (FET) has been developed and applied in various areas. However, the effective modeling and sensitivity analysis on RGO FET is still a very challenging problem due to the randomness of bandgap and density of states (DOS) in RGO. In this paper, we propose to solve the RGO FET modeling problem by integrating the data-driven thinking and the graphene FET model to develop a hybrid model. The proposed model takes advantages of the similarities between graphene and RGO to generalize the existing graphene FET model, and employs RGO FET drain-current data to characterize the specificity of the model. The basic idea in the proposed model is to modify the graphene DOS to approximate the RGO DOS so that the charge density, mobility and other parameters can be achieved through the approximated RGO DOS. We validate the model accuracy with the RGO FET based sensors that detect chemical concentrations in the aqueous environment. The RGO FET sensitivity analysis is also demonstrated to provide guidance for RGO FET application and manufacturing.

Design and investigation of the double gate TFET with heterogeneous gate dielectric using different gate materials

A 2 dimensional model of double gate hetero dielectric Tunnel Field Effect Transistor (HD-DG TFET) with hetero dielectric gate stack is carved with Silicon dioxide (SiO2) and Hafnium dioxide (HfO2) as dielectric materials. The electrical characteristics are demonstrated for the device by using 2D numerical device simulator Silvaco TCAD. The channel length, doping concentration of drain and source, thickness of device and effective oxide layer thickness of the device is kept constant throughout the work. It is showed that the proposed structure has better performance than Double Gate TFET. Also gate materials used are silver, gold, platinum and Npolysilicon. By using these materials Drain current and electric field of the device has been plotted. Also the proposed model shows a lower leakage current, better ION/IOFF ratio sub-threshold swing and lower DIBL. It has also been remarked that use of metal gate with appropriate work function along with high-k and hetero dielectric improves the carrier transport in the channel. This model aims to lower the short channel effects and give emphasis to improvement of switching ratio.

Effects of Thicknesses of Two Different Gate Insulators on the Performance of Pentacene Based Organic Field Effect Transistor

In this paper, a simulation of the electrical performance for Pentacene-based top-contact bottom-gate (TCBG) Organic Field-Effect Transistors (OFET) model with Polymethyl methacrylate (PMMA) and silicon nitride (Si3N4) as gate dielectrics was studied. The effects of gate dielectrics thickness on the device performance were investigated. The thickness of the two gate dielectric materials was in the range of 100-200nm to maintain a large current density and stable performance. MATLAB simulation demonstrated for model simulation results in terms of output and transfer characteristics for drain current and the transconductance. The layer thickness of 200nm may result in gate leakage current points to the requirement of optimizing the thickness of different layers for better performance.

Equivalent Circuit Modeling of a Dual-Gate Graphene FET

This paper presents a simple and comprehensive model of a dual-gate graphene field effect transistor (FET). The quantum capacitance and surface potential dependence on the top-gate-to-source voltage were studied for monolayer and bilayer graphene channel by using equivalent circuit modeling. Additionally, the closed-form analytical equations for the drain current and drain-to-source voltage dependence on the drain current were investigated. The distribution of drain current with voltages in three regions (triode, unipolar saturation, and ambipolar) was plotted. The modeling results exhibited better output characteristics, transfer function, and transconductance behavior for GFET compared to FETs. The transconductance estimation as a function of gate voltage for different drain-to-source voltages depicted a proportional relationship; however, with the increase of gate voltage this value tended to decline. In the case of transit frequency response, a decrease in channel length resulted in an increase in transit frequency. The threshold voltage dependence on back-gate-source voltage for different dielectrics demonstrated an inverse relationship between the two. The analytical expressions and their implementation through graphical representation for a bilayer graphene channel will be extended to a multilayer channel in the future to improve the device performance.

A Compact Current- and Voltage-Mode Model of Antenna-Coupled FET Terahertz Detectors

In this article a comprehensive modeling of cold-biased field-effect transistors (FETs) used as terahertz (THz) detectors is developed. The described model is based upon the transistor Enz-Krummenacher-Vittoz (EKV) model in order to provide valid quantities also near and below the transistor threshold by using available technology parameters, without any extra fitting nor calibration. Important aspects such as the antenna coupling and the effect of amplitude modulation of the THz source are considered in a single, handy, analytical model. THz measurements performed on specifically designed FET detectors confirm its validity, providing a powerful tool and giving a clear insight of the role of available variables. The model can anticipate time-consuming numerical simulations or more physically accurate models requiring experimental parameters calibration, that may complement the results for better accuracy.

TCAD based study of parameters affecting the electrical performance of organic thin-film transistors

Field effect transistors (FETs) are widely used in integrated circuits of electronic devices. Mostly silicon-based FETs are used for commercial purposes, but with the recent advancement in organic electronics – organic thin-film transistors (OTFTs) have become trending research topics nowadays. Modeling of organic FETs helps in understanding various electrical characteristics of the device such as on current, threshold voltage, off current, on/off ratio, and so on. Optimization of these factors is needed to enhance the working and overall performance of thin-film transistors. In this paper, the comparative study of the device having bottom-gate with electrode contact on top and bottom of organic semiconductor has been done based on the effects of organic semiconductor's thickness variation, dielectric thickness variation, and dielectric material variation on pentacene based organic transistors.

The Special Features of Simulation of the Current–Voltage Characteristics of JFETs in the Cryogenic Temperature Range

The compact models of junction field effect transistors (JFETs) used in release-quality versions of SPICE-like programs are focused only on the standard temperatures ranging from –60 to 150°C and are unworkable for an electronic circuit design in the cryogenic temperature range (below –120°C). It this study, the Low-T SPICE model of the JFET for designing electronic circuits in the extended temperature range, including the cryogenic range (from –200 to 110°С), is proposed. The model takes into account the changes in the I–V curves caused by the effect of ultralow temperature: growth of the saturation voltage VD sat, decrease of the pinch-off current Ip and steepness BETA, negative slope LAMBDA of the output I–V curves, increase of the drain–source resistance RD as the result of the freezing effect, etc. For this purpose, the dependences of the specified parameters on temperature are introduced in the model. The procedure for extracting the SPICE parameters of the Low-T SPICE model of the JFET is developed according to the results of the measurements of the standard set of the I–V curves in the cryogenic temperature range. The error of the calculation of the I–V curves is not higher than 10–15% in the temperature range from –200 to 110°C.