Metal-oxide-semiconductor Field-effect Transistors Research Articles

The correlation of the drain-source capacitance variation and the P-pillar structures in a 4H-SiC quasi super junction MOSFET

In order to improve the trade-off between the 4H-SiC planar Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and super junction MOSFET (SJ-MOSFET), particularly on the drain to source capacitance (Cds) which affects the switching performance, this study investigates the Cds of the quasi SJ-MOSFETs with various P-pillar widths, depths, and concentrations. The measured results show (1) when the N-type region between the P-pillars (Epi-1 region) is fully depleted, the Cds value abruptly drops, (2) when the N-type drift region beneath the P-pillar (Epi-2 region) is fully depleted, the slope of the Cds-Vds curve slowly changes because of the small extension of the depletion region in the P-type region. This is because the wider P-pillar width will increase the magnitude of the abrupt drop of the Cds and make the drop occur earlier; the abrupt drop of the Cds will occur later and the magnitude increases when the P-pillar depth is deeper due to the larger P-type region; Moreover, increasing the P-pillar concentration not only initiates the abrupt drop earlier and increases the magnitude, but also increases the minimum saturation value of the Cds at a higher reverse bias. This study also reveals that the mechanism of the Cds formation in a quasi SJ-MOSFET is different from the planar MOSFET and SJ-MOSFET. Finally, the simulated results are used to validate the influence of the P-pillar structures on the Cds – Vds curves in a quasi SJ-MOSFET.

A Brief Review of Single-Event Burnout Failure Mechanisms and Design Tolerances of Silicon Carbide Power MOSFETs

Radiation hardening of power MOSFETs (metal oxide semiconductor field effect transistors) is of the highest priority for sustaining high-power systems in the space radiation environment. Silicon carbide (SiC)-based power electronics are being investigated as a strong alternative for high power spaceborne power electronic systems. SiC MOSFETs have been shown to be most prone to single-event burnout (SEB) from space radiation. The current knowledge of SiC MOSFET device degradation and failure mechanisms are reviewed in this paper. Additionally, the viability of radiation tolerant SiC MOSFET designs and the modeling methods of SEB phenomena are evaluated. A merit system is proposed to consider the performance of radiation tolerance and nominal electrical performance. Criteria needed for high-fidelity SEB simulations are also reviewed. This paper stands as a necessary analytical review to intercede the development of radiation-hardened power devices for space and extreme environment applications.

The Effects of a Gate Bias Condition on 1.2 kV SiC MOSFETs during Irradiating Gamma-Radiation.

We investigated the effects of gate bias regarding the degradation of electrical characteristics during gamma irradiation. Moreover, we observed the punch through failure of 1.2 kV rated commercial Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) due to the influence of gate bias. In addition, the threshold voltage (VT) and on-resistance (Ron) of the SiC MOSFETs decreased significantly by the influence of gate bias during gamma irradiation. We extracted the concentration of carriers and fixed charge (QF) in oxide using N-type SiC MOS capacitors and Transmission Line Measurement (TLM) patterns to analyze the effects of gamma irradiation. The Total Ionizing Dose (TID) effect caused by high-energy gamma-ray irradiation resulted in an increase in the concentration of holes and QF in both SiC and oxide. To analyze the phenomenon for increment of hole concentration in the device under gate bias, we extracted the subthreshold swing of SiC MOSFETs and verified the origin of TID effects accelerated by the gate bias. The QF and doping concentration of p-well values extracted from the experiments were used in TCAD simulations (version 2022.03) of the planar SiC MOSFET. As a result of analyzing the energy band diagram at the channel region of 1.2 kV SiC MOSFETs, it was verified that punch-through can occur in 1.2 kV SiC MOSFETs when the gate bias is applied, as the TID effect is accelerated by the gate bias.

A High Channel Mobility and a Normally‐off Operation of a Vertical GaN Metal‐Oxide‐Semiconductor Field‐Effect Transistors using an AlSiO/AlN Gate Stack Structure on m‐plane Trench Sidewall

An AlSiO/AlN‐interlayer gate stack formed on c‐plane GaN metal‐oxide‐semiconductor (MOS) devices was previously developed to enhance the interface of the gate insulator. By utilizing this gate stack structure, a channel mobility of over 200 cm2 Vs−1 on c‐plane was obtained. However, the threshold voltage was negative because of the polarization charge at the AlN/GaN interface. This study extends the application of this gate stack structure to the nonpolar m‐plane, which is obtained from a trench sidewall. Both a high channel mobility of 150 cm2 Vs−1 and a threshold voltage of 1.3 V is successfully achieved, normally‐off operation. This achievement holds significant promise for the gate structure of a GaN trench‐gate MOS field‐effect transistor (MOSFET). The limiting factor of the channel mobility is Coulomb scattering in a low electric field, whereas surface roughness scattering is dominant in a higher field.

Design and implementation of pulse width modulation gate control signals for two-level three-phase inverters

The switching control circuit in a DC to AC inverter is the critical part that is applied to control the power transistors insulated-gate bipolar transistor (IGBTs) and metal-oxide semiconductor field-effect transistor (MOSFETs). This paper proposes a high-performance and low-cost pulse width modulation (PWM) control signal with a 120º phase shift circuit for a two-level three-phase inverter. Typically, a PWM signal with a 120º phase shift for three-phase inverters is generated with the help of analogue components with more complicated designs and power losses or by using a microcontroller with necessary programming or coding. The proposed solution is to design a 120° three-phase shift circuit based on D flip-flops and the 555-timer to generate the clock signal for the flip-flop input in addition to the dead-time control circuit. The proposed circuit is controlled by one square wave signal as an input signal to generate six output PWM control signals at 50 Hz to operate six MOSFETs in the three-phase inverter. Simulation results in power simulation software PSIM and PROTEUS simulation tools are used to verify the proposed circuit. Hardware implementation of the proposed circuit and three-phase inverter is carried out to validate the performance of the proposed design.

Tunneling field-effect transistors with two-dimensional BiN as the channel semiconductor

The lack of suitable channel semiconductor materials has been a limiting factor in the development of tunneling field-effect transistor (TFET) architectures due to the stringent criteria of both air stability and excellent gate-tunable electronic properties. Here, we report the performance limits of sub-10-nm double-gated monolayer (ML) BiN TFETs by utilizing first-principles quantum-transport simulations. We find that ML BiN possesses an indirect bandgap of 0.8 eV and effective masses of 0.24m0 and 2.24m0 for electrons and holes, respectively. The n-type BiN TFETs exhibit better performance than the p-type ones, and the on-state current can well satisfy the requirements of the International Roadmap for Devices and Systems for both high-performance and low-power standards. Notably, we find that the BiN TFETs exhibit distinguished gate controllability with an ultra-low subthreshold swing below 60 mV/decade even with a small gate length of 6 nm, which is superior to the existing field-effect transistors, such as black phosphorus TFETs, GeSe TFETs, and BiN metal–oxide–semiconductor field-effect transistors. Furthermore, the BiN TFETs are endowed with the potential to realize high switching speed and low-power consumption applications because of their extremely short delay time and ultra-low power-delay product. Our results reveal that the ML BiN is a highly competitive channel material for the next-generation TFETs.

4H-SiC/SiO2 Interface Degradation in 1.2 kV 4H-SiC MOSFETs due to Power Cycling Tests

Power cycling tests (PCTs) assess the reliability of power devices by closely simulating their operating conditions. A PCT was performed on commercially available 1.2 kV 4H-SiC power metal–oxide–semiconductor field-effect transistors to observe its impact on the 4H-SiC/SiO2 interface. High-resolution transmission electron microscopy and electron energy loss spectroscopy measurements showed variations in the length of the 4H-SiC/SiO2 transition layer, depending on whether the device was power cycled. Moreover, the total resistance at Vg >> Vt in Rtot − (Vg-Vt)−1 graph increased to 16.5%, while it changed more radically to 47.3% at Vg ≈ Vt. The threshold voltage shifted negatively. These variations cannot be expected solely through the wearout of the package.

An investigation into the short-circuit characteristics of Sic MOSFET power devices

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) devices exhibit substantial prospects for application under extreme operational conditions, including elevated temperatures, high voltages, and high frequencies. Nevertheless, owing to their distinctive material and structural attributes, SiC MOSFET devices are not devoid of challenges, with the short-circuit phenomenon constituting a pivotal avenue of inquiry. The short-circuit effect pertains to the abrupt escalation of leakage current that these devices might undergo under elevated voltage conditions, thereby exerting a perturbing influence on their stability and reliability. Investigations into the short-circuit effect predominantly revolve around two dimensions: one involves comprehending its underlying physical mechanisms, while the other centers on identifying commensurate remedial approaches.With respect to the underlying physical mechanisms, researchers have discerned that the elevated breakdown field strength and augmented carrier mobility intrinsic to SiC materials engender an augmentation in leakage current, consequently giving rise to the short-circuit effect. Furthermore, factors such as oxide layer anomalies and surface states are also conceivable catalysts for the surge in leakage current. To rectify this predicament, scholars have proffered a panoply of stratagems, encompassing the optimization of material synthesis processes, enhancement of oxide layer quality, refinement of device structural designs, and incorporation of protective circuitry, among others. In summation, the investigation of the short-circuit effect in silicon carbide MOSFET devices is fundamentally aimed at attaining an in-depth comprehension of its causative mechanisms. Moreover, it endeavors to proffer efficacious resolutions conducive to augmenting the reliability and steadfastness of these devices within high-temperature and high-voltage environments, thereby facilitating their widespread integration within the ambit of high-performance power electronics.

Innovations in thin‐film electronics for the new generation of displays

AbstractToday's display industry faces transistor‐level challenges similar to those of complementary metal‐oxide semiconductor (CMOS) metal‐oxide semiconductor field‐effect transistors (MOSFETs) in the mid‐1990s. Learnings from MOSFETs inform the display industry's response to the limitations of silicon‐based thin‐film transistors (TFTs). Improvements sustaining Moore's Law drove the need to rethink MOSFET materials and structures. The display industry needs fundamental innovation at the device level. New thin‐film devices enable an inflection point in the use of displays, just as fin field‐effect transistor (FinFET) defined the inflection point in CMOS in the 2000s. This paper outlines two innovations in thin‐film device technology that offers improvement in image quality and power consumption of flat panel displays: amorphous metal gate TFTs (AMeTFTs) and amorphous metal nonlinear resistors (AMNRs). Linked through a single core material set based on mass‐producible, thin‐film amorphous metals, these two innovations create near‐ and long‐term roadmaps simplifying the production of high‐image quality, low‐power consumption displays on glass (now) and plastic (future). In particular, the field‐effect mobility of indium gallium zinc oxide (IGZO) AMeTFTs (55–72 cm2/Vs) exceeds that of IGZO TFTs developed by existing display manufacturers without the need for atomic layer deposition or vertical stacking of heterostructure semiconductor films, making AMeTFTs a natural choice for the new G8.5–G8.7 fabs targeting IGZO backplanes.

Physical Insights into THz Rectification in Metal–Oxide–Semiconductor Transistors

Metal–oxide–semiconductor field-effect transistors (MOSFETs) have proven to be effective devices for rectifying electromagnetic radiation at extremely high frequencies, approximately 1 THz. This paper presents a new interpretation of the THz rectification process in the structure of an MOS transistor. The rectification depends on the nonlinear effect of the carrier dynamics. The paper shows that the so-called self-mixing effect occurs within the interface region between the source and the channel. The basic tool used numerical TCAD simulations, which offer a direct interpretation of different aspects of this interaction. The complex, 2D effect is examined in terms of its basic aspects by comparing the MOS structure with a simplified case study structure. We demonstrate that a contribution to the output-rectified voltage detectable at the drain arises from the charging of the drain well capacitance due to the diffusion of excess electrons from the self-mixing interaction occurring at the source barrier. In addition, the paper provides a quantitative description of the rectification process through the definition of the output equivalent circuit, offering a new perspective for the design of detection systems.

From MOSFET to FinFET to GAAFET: The evolution, challenges, and future prospects

With the swift progression of semiconductor technology, the transition from Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) to Fin Field-Effect Transistors (FinFETs) and further to Gate-All-Around Field-Effect Transistors (GAAFETs) presents significant potential for the future of electronic devices and systems. This article delves into the intricate applications, challenges, and prospective evolutions associated with FinFET and GAAFET technologies. Findings suggest that these technologies are particularly apt for low-power logic systems, high-performance computing, and artificial intelligence domains. However, as dimensions shrink, challenges pertaining to heat dissipation, leakage, and manufacturing consistency become prominent. Despite these hurdles, the horizon for semiconductor technology remains bright, encompassing exploration of alternative materials such as Germanium and 2D compositions and innovative designs like U-shaped Field-Effect Transistors and Complementary Field-Effect Transistors. As the industry continues its relentless pursuit of even more efficient, smaller transistors, the exploration of alternative materials and diversification in architecture may play a pivotal role in future developments. In essence, while the semiconductor sphere confronts challenges, relentless innovation promises a future brimming with even more efficient and compact transistor technologies.

Modeling of Charge-to-Breakdown with an Electron Trapping Model for Analysis of Thermal Gate Oxide Failure Mechanism in SiC Power MOSFETs.

The failure mechanism of thermal gate oxide in silicon carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs), whether it is field-driven breakdown or charge-driven breakdown, has always been a controversial topic. Previous studies have demonstrated that the failure time of thermally grown silicon dioxide (SiO2) on SiC stressed with a constant voltage is indicated as charge driven rather than field driven through the observation of Weibull Slope β. Considering the importance of the accurate failure mechanism for the thermal gate oxide lifetime prediction model of time-dependent dielectric breakdown (TDDB), charge-driven breakdown needs to be further fundamentally justified. In this work, the charge-to-breakdown (QBD) of the thermal gate oxide in a type of commercial planar SiC power MOSFETs, under the constant current stress (CCS), constant voltage stress (CVS), and pulsed voltage stress (PVS) are extracted, respectively. A mathematical electron trapping model in thermal SiO2 grown on single crystal silicon (Si) under CCS, which was proposed by M. Liang et al., is proven to work equally well with thermal SiO2 grown on SiC and used to deduce the QBD model of the device under test (DUT). Compared with the QBD obtained under the three stress conditions, the charge-driven breakdown mechanism is validated in the thermal gate oxide of SiC power MOSFETs.

Three‐phase common‐ground‐type photovoltaic inverter without shoot‐through problem

SummarySince there are common mode leakage current (CMLC) and shoot‐through problems in the conventional three‐phase transformerless photovoltaic (PV) inverters, the three‐phase common‐ground‐type transformerless dual‐buck inverters (DBIs) are derived. By shorting the neutral point of the three‐phase load and the negative terminal of the PV panel, the CMLC is eliminated. The DBIs has no shoot‐through problem and there is no current flowing through the body diode of the SiC metal oxide semiconductor field‐effect transistor (MOSFET). The three‐phase DBI combined with a buck‐boost converter is taken as an example to illustrate the operating principle of the derived inverters. The control strategy of the inverter is given. A prototype is built to validate the proposed inverter. Finally, comparison among the proposed inverter and other three‐phase inverters is given.

Performance Improvement of a ZnGa2O4 Extended-Gate Field-Effect Transistor pH Sensor.

ZnGa2O4 sensing films were prepared using an RF magnetron sputtering system and connected to a commercial metal oxide semiconductor field-effect transistor (MOSFET) as the extended-gate field-effect transistor (EGFET) to detect pH values. Experimental parameters were adjusted by varying the oxygen flow rate in the process chamber to produce ZnGa2O4 sensing films with different oxygen ratios. These films were then treated in a furnace tube at an annealing temperature of 700 °C. The sensitivity and linearity of the constant current mode and the constant voltage mode were measured and analyzed in the pH range of 2-12. Under the deposition conditions with an oxygen ratio of 6%, the sensitivity reached 23.14 mV/pH and 33.49 μA/pH, with corresponding linearity values of 92.1 and 96.15%, respectively. Finally, the sensing performance of the ZnGa2O4 EGFET pH sensor with and without annealing processes was analyzed and compared.

Investigation of dual work function metal (DWFM) gate stacks with ALD TaAlN and TaAlC for multi threshold voltages (VTHs) engineering in MOS device integration

This study investigates methods to modulate the effective work function (EWF) and control the multiple threshold voltages (VTHs) of metal-oxide-semiconductor (MOS) devices by applying metal electrodes with different work function materials (WFMs), including a single layer of n-type (TaAlC) and p-type (TaAlN) as well as their stacked structures, through atomic layer deposition (ALD). Dual-Work-Function-Metal (DWFM) gate is a crucial aspect of confirming the feasibility of metal gate stacks in MOS devices for a complementary metal-oxide-semiconductor (CMOS) integration scheme. The gate stack structure of p-Si/IL (Inter layer)/HfO2/DWFM (p/n-type compatible metal stack)/W exhibits good adhesion and even chemical composition distribution, as evidenced by transmission electron microscope (TEM) and energy dispersive spectrometer (EDS) analysis. By fabricating MOS capacitors using this WFM structure and extracting EWF from the measured capacitance-voltage (C–V) characteristics, EWF values of 4.62 eV and 4.99 eV were identified both before and after annealing using forming gas, indicating pWFM-like properties. These properties are attributed to the strengthened Al–O bonds and reduced CO peaks seen in x-ray photoelectron spectroscopy (XPS) analysis. The use of different Ta precursor from Tris(diethylamido)(tert-butylimido)tantalum(V) (TBTDET) as well as TaCl5 resulted in the increase of the EWF following the unique p-WFM like feature. As candidates for WFM electrode in metal-oxide-semiconductor field effect transistor (MOSFET) with the DWFMs (n/p stacks) were evaluated, resulting in a VTH of 0.84 V that places in the middle of the VTH shift range from 0.6 V (nWFM) to 1.16 V (pWFM), approximately. The DWFMs allow for modulation of the EWF, which in turn reduces ambiguity in addressing replacement metal gate (RMG) challenges and opens up new avenues for achieving multi-VTH solutions in CMOS integration schemes.

Non-equilibrium Green's function analysis of charge plasma-based source-drain electrode P-type MoTe2 MOSFET for high sensitivity hydrogen sensing

—The paper presents a novel P-type molybdenum ditelluride (MoTe2) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) designed for high sensitivity hydrogen sensing applications. Through the utilization of palladium at the source-drain charge plasma electrode, P+ regions at both ends are generated, obviating the necessity for low-dimensional MoTe2 doping. Simultaneously, the inclusion of palladium on both regions act as the sensing area, resulting in notably heightened sensitivity. The study employs Non-Equilibrium Green's Function (NEGF) formalism to investigate the carrier transport properties of the device. The results provide valuable insights into less explored area of p-type MOSFET performance as Hydrogen(H2) gas sensor and its potential.

Effect of the column design and fabrication method on the reverse recovery characteristics of 1.2 kV SiC-superjunction-MOSFETs

We investigated the effects of the column length and fabrication method of the superjunction (SJ) structure on the reverse recovery characteristics of 1.2 kV silicon carbide (SiC) SJ metal–oxide–semiconductor field-effect transistors (MOSFETs). The voltage slope (dV/dt) and reverse recovery current slope (dir/dt) values during the reverse recovery of the SJ-MOSFETs with the SJ structure formed by Aluminum (Al) ion implantation were comparable to the values of MOSFETs without SJ structure at room temperature (RT), but they increased markedly with temperature. This is caused by the reduced p-column carrier concentration at RT during short recovery transient time due to the deep hole trap (DI center) introduced by ion implantation. At 175 °C, a softer reverse recovery waveform was obtained by shortening the SJ columns. Besides, Al ion implanted SJ-MOSFETs exhibited a weaker current dependence of the reverse recovery charge Qrr at 175 °C indicating a lower carrier injection level compared to the SJ-MOSFETs with the SJ structure formed by trench formation and epitaxial growth. This is caused by the short carrier lifetime of the SJ columns due to the Al ion implantation defects. The short and Al ion implanted SJ columns are effective for soft reverse recovery characteristics in SiC-SJ-MOSFETs.

Revolutionizing Technology with Spintronics: Devices and Their Transformative Applications

The scaling of metal oxide semiconductor field effect transistors (MOSFETs) for data storing and logic circuit operation has reached a critical point, beyond which further scaling poses various secondary issues. These problems include short channel effects, hot carrier effects (HCEs), and reliability concerns. However, a promising alternative called spintronics has recently emerged as a highly exciting technology. Spintronics considers both the charge and spin of electrons in device operations and offers superior properties compared to MOSFETs.Researchers have reported numerous spintronics devices that exhibit significant potential in memory and logic circuits when integrated with complementary metal oxide semiconductor (CMOS) technology. These devices not only possess excellent scalability but also consume less power than MOSFETs at the nano-scale level. This article aims to provide a comprehensive review of the current state, future prospects, and challenges associated with spintronics devices.

Carrier injection induced degradation of nitrogen passivated SiC–SiO2 interface simulated by time-dependent density functional theory

The performance of SiC-based metal-oxide-semiconductor field-effect transistors (MOSFETs) degrades seriously after a period of continuous operation. To directly understand this issue, we conduct real-time time-dependent density functional theory (TDDFT) simulations on a series of nitrogen passivated SiC–SiO2 interfaces to monitor the interaction between carriers and interface atoms. We find that the nitrogen passivation always leaves behind two local states near the VBM, which gives a chance to the strong interaction between channel carriers and C–N bonds, and finally results in the generation of C dangling bond defects. These processes are vividly presented and confirmed by the TDDFT simulation. Additionally, the results show that the new defects are more easily formed by the passivated C cluster than the passivated Si vacancy. These studies provide physical insights into the degradation mechanisms of working SiC MOSFETs, while simultaneously demonstrating the advantage of TDDFT as a crucial tool for investigating defect generation dynamics in semiconductor devices.

Research and analysis of electromagnetic interference of a motor drive control system based on PMSM with SiC MOSFET for new energy electric vehicles

Sustainable development in the 21st century faces significant challenges due to finite reserves of fossil fuels and environmental pollution. In the context of new energy electric vehicles (NEEVs), the wide-bandgap semiconductor known as the silicon carbide–metal oxide–semiconductor field-effect transistor (SiC MOSFET) and the permanent magnet synchronous motor (PMSM) have emerged as advantageous sources. However, the use of these components gives rise to electromagnetic interference (EMI) issues, which impede the achievement of electromagnetic compatibility (EMC) standards in the motor drive control system. This paper aims to elucidate the generation mechanism, propagation path, and test infrastructure of EMI. Furthermore, it proposes a system-level conducted EMI equivalent circuit model for the motor drive control system, encompassing the power battery pack, busbar cable, LISN, three-phase inverter, and PMSM. Building upon this foundation, the principles for suppressing and optimizing EMI noise are discussed. The paper concludes with the validation of simulations and experimental results, which demonstrate the effectiveness of the proposed approach. It is anticipated that professionals with an interest in the field of EMI/EMC will find this paper to be of both theoretical and practical importance.