The correlation of the drain-source capacitance variation and the P-pillar structures in a 4H-SiC quasi super junction MOSFET

Abstract

In order to improve the trade-off between the 4H-SiC planar Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and super junction MOSFET (SJ-MOSFET), particularly on the drain to source capacitance (Cds) which affects the switching performance, this study investigates the Cds of the quasi SJ-MOSFETs with various P-pillar widths, depths, and concentrations. The measured results show (1) when the N-type region between the P-pillars (Epi-1 region) is fully depleted, the Cds value abruptly drops, (2) when the N-type drift region beneath the P-pillar (Epi-2 region) is fully depleted, the slope of the Cds-Vds curve slowly changes because of the small extension of the depletion region in the P-type region. This is because the wider P-pillar width will increase the magnitude of the abrupt drop of the Cds and make the drop occur earlier; the abrupt drop of the Cds will occur later and the magnitude increases when the P-pillar depth is deeper due to the larger P-type region; Moreover, increasing the P-pillar concentration not only initiates the abrupt drop earlier and increases the magnitude, but also increases the minimum saturation value of the Cds at a higher reverse bias. This study also reveals that the mechanism of the Cds formation in a quasi SJ-MOSFET is different from the planar MOSFET and SJ-MOSFET. Finally, the simulated results are used to validate the influence of the P-pillar structures on the Cds – Vds curves in a quasi SJ-MOSFET.