Metal Oxide Semiconductor Transistors Research Articles

Energy Efficient Digital Circuits using Two Phase Clocking Sub-Threshold Adiabatic Logic

Power is a major constraint in Digital VLSI circuits, due to reduction in sizes of Metal Oxide Semiconductor (MOS) transistors are scaling down. Low-power technologies are used to diminish the power utilization be able to be classified as Sub-threshold CMOS and Adiabatic logic tachniques. In, Sub-threshold CMOS defines a system which reduces the power utilization to inferior than the threshold voltage of a MOS Device, where as Adiabatic logic circuit is a method which minimizes the energy usage through suppress the applied voltage to the resistance of a given VLSI design. This effort deals to offer a subthreshold adiabatic logic circuit of low power CMOS circuits that uses 2φ clocking subthreshold Adiabatic Logic. The digital circuits were designed in HSPICE using 0.18 μm CMOS standard process technology. It is evident from the results that the 2φ Clocking Subthreshold Adiabatic design is beneficial in major application where power starving is of major significance at the same time as in elevated its performance efficiency in DSP processor IC, System on chip, Network on chip and High speed digital ICs.

Charge Pumping Under Spin Resonance in Si(100) Metal-Oxide-Semiconductor Transistors

Gate-pulse-induced recombination, known as the charge pumping (CP), is a fundamental carrier recombination process, and has been utilized as a method for analyzing electrical properties of defects (or dangling bonds) at the transistor interfaces, which is now recognized to be well-matured and conventional. Nevertheless, neither the origin (the bonding configuration) of the defects responsible for the CP, nor their detailed recombination sequence has been clarified yet for Si metal-oxide-semiconductor (MOS) interfaces. In order to address these problems, we investigated the CP under spin resonance conditions at temperatures ranging from 27 to 300 K in Si(100) n-type MOS transistors. We obtained evidence that Pb0 and E' centers, the two major dangling bonds at (and near) the Si(100) interface, participate in the CP recombination process. We also show that the spin-dependent CP process is explained by the formation of electron-electron spin pairs, which in turn reveals that the CP via Pb0 and E' centers is inherently a two-electron process.

Single transistor fractional-order filter using a multi-walled carbon nanotube device

A low-pass fractional-order filter topology based on a single metal oxide semiconductor transistor is presented in this Letter. The filter is realized using a fractional-order capacitor fabricated using multi-walled carbon nanotubes. The electronic tuning capability of the filter’s frequency characteristics is achieved through a biasing current source. Experimental results are presented and compared with the theory.

A 600-V Super-Junction pLDMOS Utilizing Electron Current to Enhance Current Capability

In this paper, a super-junction p-type lateral diffused metal–oxide–semiconductor transistor (SJ-pLDMOS) utilizing electron to enhance the current capability is proposed. The proposed SJ-pLDMOS has an n-channel in the drain region and is controlled by an auto-generated voltage signal ( ${V}_{\mathrm {\textsf {Gn}}}$ ). The voltage signal ${V}_{\mathrm {\textsf {Gn}}}$ is generated during the ON- and OFF-state of the hole current which flows across an integrated resistor ( ${R}\text{p}$ ) implemented in the p-base region. Thus, the proposed SJ-pLDMOS utilizes both hole and electron currents to significantly enhance the current capability. Simulation results show that the current capability of the proposed SJ-pLDMOS without any conductivity modulation effect is comparable with that of a super-junction nLDMOS (SJ-nLDMOS). The total power loss of the proposed super-junction pLDMOS (SJ-pLDMOS) is reduced by about 26.7% and 18% compared with that of the SJ-nLDMOS and Triple Resurf nLDMOS (TR nLDMOS) at a rated load current density of $25~\mu \text{A}/\mu \text{m}$ , respectively.

Prediction of Stable and High-Performance Charge Transport in Zigzag Tellurene Nanoribbons

The 2-D materials possess application perspective in semiconductor logic devices owing to their bonding free surface carrier transport. However, the scaling transistor width-induced edge issues have significantly limited their surface transport within the lateral direction, leading to effective mass increasing, and bandgap fluctuations. Therefore, it is important to find a novel 2-D material with both excellent surface transport and immunity to edge effect. In this paper, inspired by the recently discovered tellurene and its unique Te-Te bonds, the edge effect on the transport characteristics of tellurene is studied theoretically in the form of tellurene nanoribbons (TNRs). Among the four edge types, three of them exhibit semiconducting characteristic owing to the unique bonding property of Te. Simulation results demonstrate that the tetragonal edges (TEs) in zigzag TNRs (ZTNRs) almost have no influence on surface transport, resulting in minimized bandgap and effective mass variations, compared to that of graphene nanoribbons, and Si and Ge nanowires. Transport behaviors of the TE-ZTNRs are investigated using a metal–oxide–semiconductor transistor model and a multiscale simulation flow, with the calculated current densities exceeding $\textsf {1}$ mA/ $\mu \text{m}$ and the on–off ratios over $10^{\textsf {11}}$ . Based on the results, an explicit prediction that the TE-ZTNRs are competitive candidates for nanoscale transistor materials is proposed.

Change-point analysis of the failure mechanisms based on accelerated life tests

In the accelerated life tests, the common failure mechanism is considered as a necessary condition for the extrapolated procedure. The traditional extrapolation model may become unreliable if the failure mechanisms under the accelerated stress levels are different from that under the normal operating condition. In this paper, we propose a change-point model for the coefficients of variation to fit the abrupt change behavior of the failure mechanisms with a nonparametric empirical likelihood approach. The related statistical inferences of the proposed model are studied to test whether there exists a change and estimate the corresponding location of the change. Monte Carlo simulations are conducted to investigate the performance of the proposed change-point test model. For the small sample data, a bootstrapping method is presented as an alternative detecting procedure. The detailed calculation process is illustrated by the lifetime data of the metal oxide semiconductor transistors in the power distribution system of Chinese Tiangong aircrafts.

Circuit Implementation of Nano-Scale TiO2 Memristor Using Only Metal-Oxide-Semiconductor Transistors

A metal-oxide-semiconductor (MOS)-based circuit model that emulates a TiO2 memristor is proposed in this study. First, a TiO2 (10-nm active layer thickness)-based memristor device was fabricated. The structural properties of the device were confirmed via energy dispersive X-ray spectroscopy. The memristive characteristics of the device were resolved by applying a time-dependent voltage. The typical pinched hysteresis memristive loops of the current-voltage curves were obtained. After physical implementation and characterization of the device, a circuit model was implemented using only four MOS transistors to emulate the fabricated TiO2 memristor. In addition to emulating the fabricated memristor, the proposed circuit model is suitable for use in general memristor-based applications. No active element or circuit blocks were used in the circuit to achieve memristive characteristics. The simulation and experimental results are in good agreement; moreover, the circuit is very simple compared to those presented in previous studies in the literature and it was able to emulate the fabricated memristor. All simulations were completed using 180 nm TSMC CMOS process parameters.

Analysis of Memory Matrices with HfO2 Memristors in a PSpice Environment

The investigation of new memory circuits is very important for the development of future generations’ non-volatile and Random Access Memories (RAM) memories and modern schemes for in-memory calculations. The purpose of the present research is to propose a detailed analysis of passive and hybrid memristor-based memory crossbars with separating metal oxide semiconductor (MOS) transistors. The considered memristors are based on HfO2. The transistors are applied to eliminate the parasitic paths in the schemes. For simulations, a previously proposed strongly nonlinear modified window function by the author together with a physical nonlinear memristor model is used. The considered model is adjusted according to the experimental i–v relationship of HfO2 memristors. The i–v relationship obtained by the simulation is successfully fitted to the respective relationship derived by physical measurements. A good coincidence between these characteristics is established. Several basic window functions are also applied for comparison to the corresponding results. The proposed model is analyzed in Personal Simulation Program with Integrated Circuit Emphasis (PSpice) and it is also used for simulation of a 5 × 5 fragment of a memristor memory crossbar with isolating transistors and for the analysis of a 6 × 6 passive memory matrix. The investigated matrices are simulated for writing, reading, and erasing information. It is established that the model proposed could be used for simulations of complex memristor circuits.

Compact Modeling of Fin-LDMOS Transistor Based on the Surface Potential

One of the basic components of smart power integrated circuits (SPICs) is the laterally diffused metal oxide semiconductor (LDMOS) transistors. In this paper, we propose Fin-LDMOS transistor based on the surface potential. In order to improve the accuracy, we have taken into account not only the fin-shape structure of the gate but also the mobility reduction and saturation velocity. The proposed method is evaluated considering a broad range of biases and physical parameters of the device. The comparison between modeling results and 3D simulations confirm the remarkable accuracy of our model.

Mitigation of Threshold Voltage Shift Due to Negative Bias Temperature Instability by Exploiting Solgel-Derived TiO2 Incorporation

To ensure reliability inside complementary metal oxide semiconductor transistors, the results on the basis of negative bias temperature instability by incorporating aged TiO2 gels on SiO2 dielectric have been reported. TiO2 was chosen for the incorporation. Precursor aging has been carried out for 2, 3 and 4 days. Samples with maximum dielectric constant after aging and UV treatment were extracted. Under DC stress, exploiting cured sample (4 days aged and 3 h UV exposed) of TiO2 results in a 70% (70% decrease in threshold voltage) increase in drain current. Under AC or dynamic bias stress, exploiting cured sample (4 days aged and 3 h UV exposed) of TiO2 results in a 65% increase (65% decrease in threshold voltage).

Effect of the Electric Mode and γ Irradiation on Surface-Defect Formation at the Si–SiO2 Interface in a MOS Transistor

The results of experimental investigation into surface-defect formation under the effect of gamma-radiation with a dose rate P = 0.1 rad(Si)/s on MOS (metal-oxide-semiconductor) transistors with the n-type channel in the passive and active modes are presented. Two stages of surface-defect formation are observed. A qualitative model is proposed to explain the effect of the the drain transistor voltage on the defect formation process.

Investigation of RF and linearity performance of electrode work‐function engineered HDB vertical TFET

This work realises a hetero-dielectric buried oxide vertical tunnel held effect transistor (HDB VTFET) and investigates its radio frequency (RF) and linearity characteristics. First time, the concept of hetero-dielectric buried oxide (BOX) in VTFET is used to obtain the superior improvement in terms of different RF and linearity hgure of merits such as C gs , C gd , C gg , f T , Gain Bandwidth Product (GBP), t, Transconductance Frequency Product (TFP), Transconductance Generation Factor (TGF), g m2 , g m3 , VIP 2 , VIP 3 , IIP 3 , IMD 3 and 1-dB compression point. Also, the influence of HfO2 BOX length scaling on these FOMs is analysed. The results reveal that the HDB VTFET can be a promising contender to replace bulk metal-oxide semiconductor held-effect transistors in analogue/mixed signal system-on-chip and high-frequency microwave applications and the accuracy of this device is validated by TCAD Sentaurus simulator.

Влияние электрического режима и γ-облучения на образование поверхностных дефектов на границе раздела Si-SiO-=SUB=-2-=/SUB=- в МОП-транзисторе

AbstractThe results of experimental investigation into surface-defect formation under the effect of gamma-radiation with a dose rate P = 0.1 rad(Si)/s on MOS (metal-oxide-semiconductor) transistors with the n -type channel in the passive and active modes are presented. Two stages of surface-defect formation are observed. A qualitative model is proposed to explain the effect of the the drain transistor voltage on the defect formation process.

Negative Capacitance Transistors

In recent years, the negative capacitance effect in ferroelectric (FE) materials has attracted significant attention from many researchers around the world. The negative capacitance effect promises to reduce the voltage requirement in conventional complementary metal–oxide–semiconductor transistors below what is otherwise believed to be the Boltzmann limit. In this paper, our objective is to discuss the fundamental underpinning of the negative capacitance effect and describe how it can be utilized for transistors. We shall start with a thermodynamic perspective to understand where the reduction in energy dissipation comes from. We then proceed to derive the S curve in an FE material from fundamental principles. The central result of this paper is to associate the negative slope region in the S curve to a physically definable configuration of dipoles in the crystal structure. The design of a negative capacitance transistor is essentially an exercise of stabilizing the FE in the negative slope region of the S curve using the semiconductor capacitance as a series capacitor.

Analysis and Simulations of Hybrid Memory Scheme Based on Memristors

The investigation of new memory schemes is significant for future generations of electronic devices. The purpose of this research is to present a detailed analysis of the processes in the memory elements of a memory section with memristors and isolating Metal Oxide Semiconductor (MOS) transistors. For the present analysis, a modified window function previously proposed by the author in another memristor model is used. The applied model is based on physical nonlinear current-voltage and state-voltage characteristics. It is suitable for illustration of the processes in the memristors for both writing and reading procedures. The memory scheme is simulated using a nonlinear drift model with an improved window function. The used model was previously adjusted according to the reference Pickett model. The memory circuit is analyzed for writing and reading information procedures. The memristor current-voltage relationship is compared to physical experimental characteristics and to results acquired by the use of basic window functions. A satisfactory coincidence between the corresponding results is established. For the used logical signals, the memory elements operate in a state near to hard-switching mode. It is confirmed that the memristor model with a modified window function applied here is suitable for investigating complex memristor circuits for a general operating mode.

0.65 V integrable electronic realisation of integer‐ and fractional‐order Hindmarsh–Rose neuron model using companding technique

Some neurons like neocortical pyramidal neurons adapt with multiple time-scales, which is consistent with fractional-order differentiation. The fractional-order neuron models are therefore believed to portray the firing rate of neurons more accurately than their integer-order models. It has been studied that as the fractional order of differentiator and integrator involved in the neuron model decreases, bursting frequency of the neurons increases. The opposite effect has been observed on increasing the external excitation. In this study, integer- and fractional-order Hindmarsh–Rose (HR) neuron models have been implemented using sinh companding technique. Besides, the application of the HR neuron model in a simple network of two neurons has also been considered. The designs offer a low-voltage and low-power implementation along with the electronic tunability of the performance characteristics. Due to the use of only metal-oxide semiconductor (MOS) transistors and grounded capacitors, the proposed implementation can be integrated in chip form. On comparing with existing implementations, the implemented fractional-order and integer-order models show a better performance in terms of power consumption, supply voltage, order and flexibility. The performance of the circuits has been verified using 130 nm complementary MOS (CMOS) technology process provided by Austrian Micro Systems using HSPICE simulation software.

Neurospace Mapping Modeling for Packaged Transistors

This paper presents a novel Neurospace Mapping (Neuro-SM) method for packaged transistor modeling. A new structure consisting of the input package module, the nonlinear module, the output package module, and the S-Matrix calculation module is proposed for the first time. The proposed method can develop the model only using the terminal signals, instead of the internal and physical structure information of the transistors. An advanced training method utilizing the different parameters to adjust the different characteristics of the packaged transistors is developed to make the proposed model match the device data efficiently and accurately. Measured data of radio frequency (RF) power laterally diffused metal-oxide semiconductor (LDMOS) transistor are used to verify the capability of the proposed Neuro-SM method. The results demonstrate that the novel Neuro-SM model is more accurate and efficient than existing device models.

A provable key destruction scheme based on memristive crossbar arrays

Digital keys are commonly used in today’s hardware security systems. However, the provable destruction of these keys after use remains a challenging problem. Most security primitives built using traditional complementary metal–oxide–semiconductor transistors are not well suited to address this issue because of their volatility and unreliability at small scales. Here we show that the unique physical fingerprint of a 128 × 64 hafnium oxide memristor crossbar array integrated with transistors is capable of provable key destruction. The fingerprint is extracted by comparing the conductance of neighbouring memristors, and it can be revealed only if a digital key stored on the same array is erased. On the basis of this provable key destruction technique, we propose a protocol for logic locking/unlocking that can support secure outsourcing of integrated circuit manufacturing. By leveraging the unique properties of memristors, including reconfigurability and variability, our chip demonstrates the integration of security, memory and computing functionalities into the same circuits, and could be used to develop more secure, compact and efficient memristive hardware systems. A hafnium oxide memristor crossbar array integrated with transistors can provide a provable key destruction scheme in which unique physical fingerprints are extracted by comparing the conductance of neighbouring memristors, and can only be revealed if a digital key stored on the same array is erased.

Switch-OFF Avalanche-Breakdown-Induced Electrical Degradations of RF-LDMOS Transistor for SMPAs Applications

The electrical parameters degradations of a radio frequency lateral-diffused metal–oxide–semiconductor transistor under switch-OFF avalanche breakdown stress have been first experimentally investigated. A modified three-port dc-IV method is proposed to demonstrate the degradation mechanisms. It shows that the interface states generation under the edge of the polygate at the n-drift region brings the increase in ON-resistance due to the decrease in carrier mobility, while the hot-holes injection and trapping there leads to the increase in gate–drain capacitance due to the widening restriction of the depletion layer in the n-drift region. Furthermore, the output power and the power gain are also decreased under the avalanche shocks. However, other electrical parameters, such as threshold voltage, gate–source capacitance, and drain–source capacitance, can be kept unchanged.

Low power and high speed design issues of CMOS Hamming code generation and error detection circuit at 22 nm and 16 nm channel length of MOS transistor

This paper represents low power and high speed design issues of Hamming code generation and error detection circuit using complementary metal oxide semiconductor (CMOS) technology. Average power consumption and input to output gate delay for both Hamming code generation and error detection circuit are analyzed at 22 nm and 16 nm channel length of Metal Oxide Semiconductor (MOS) transistor. The functionality of the circuits are clarified using Tanner SPICE (T-SPICE) software. The average power consumption and input to output gate delay of the circuits are reported considering the parameters—power supply voltage, channel width to length ratio of transistors. It has been observed that whenever power supply voltage (VDD) increases, power consumption across the circuits increases, however gate delay decreases for both the circuit for fixed channel width to length ratio of the transistors. On the other hand, for fixed value of VDD if channel width to length ratio of NMOS transistor increases gate delay decreases however average power consumption increases. The variation of average power consumption and delay has also been reported with respect to KPN ratio. KPN is the ratio of channel width to length ratio of PMOS transistor to channel width to length ratio of NMOS transistor. Average power consumption is more for higher value of KPN ratio. In contrast gate delay is less at higher value KPN ratio. In this work, the values of average power consumption and gate delay are of the order of microwatt and picosecond respectively. The average power consumption of the Hamming code generation circuit in this work at 0.8 V of VDD is 0.2 µW and 1.3 µW for 22 nm and 16 nm cannel length of MOS transistor respectively. Whereas at the VDD of 0.8 V, the average power consumption of the error detection circuit is 0.4 µW and 2.3 µW respectively for 22 nm and 16 nm cannel length. The gate delay of the Hamming code generation circuit in this work at VDD of 0.8 V is 4.7 ps and 3.3 ps for for 22 nm and 16 nm cannel length of MOS transistor respectively. Also at the VDD of 0.8 V, the gate delay of the error detection circuit has been reported in this work is 16.4 ps and 12.5 ps for 22 nm and 16 nm channel length respectively. Therefore for low power and high speed Very Large Scale Integrated (VLSI) circuit design this work is applicable.