Metal Gate Application Research Articles

Effect of Annealing Temperature on Microstructure and Resistivity of TiC Thin Films

Titanium carbide (TiC) thin films were prepared by non-reactive simultaneous double magnetron sputtering. After deposition, all samples were annealed at different temperatures under high-vacuum conditions. This paper mainly discusses the influence of deposition methods and annealing temperatures on microstructure, surface topography, bonding states and electrical resistivity of TiC films. XRD (X-ray diffraction) results show that TiC thin films can still form crystals without annealing, and the crystallinity of thin films is improved after annealing. The estimated grain size of the TiC films varies from 8.5 nm to 14.7 nm with annealing temperature. It can be seen from SEM (scanning electron microscope) images that surfaces of the films are composed of irregular particles, and when the temperature reaches to 800 °C, the shape of the particles becomes spherical. Growth rate of film is about 30.8 nm/min. Oxygen-related peaks were observed in XPS (X-ray photoelectron spectroscopy) spectra, which is due to the absorption of oxygen atoms on the surface of the film when exposed to air. Raman spectra confirm the formation of TiC crystals and amorphous states of carbon. Resistivity of TiC films decreases monotonically from 666.73 to 86.01 μΩ·cm with the increase in annealing temperature. In brief, the TiC thin films prepared in this study show good crystallinity, thermal stability and low resistivity, which can meet the requirements of metal gate applications.

(Invited) Combined Gas Cluster Ion Beam (GCIB) and Chemical-Mechanical Planarization (CMP) Process for Replacement Metal Gate (RMG) Application

The introduction of high-k metal gate (HK/MG) stack has enabled the resumption of Moore’s Law at the 45/32nm nodes, when the conventional Poly/SiON gate stacks failed to meet the required scaled-down performance targets. Despite the well demonstrated benefits such as reduced gate leakage, HK/MG integration scheme itself brings about new challenges in Si-based semiconductor process technologies. Among them, the most critical and stringent step is RMG CMP, which is tasked to deliver gate height uniformity within the range of a few nanometers on all chips across the entire 300mm wafer for 14nm technology nodes and beyond. Conventional approaches to CMP planarity and uniformity often include the optimization of carrier zone pressure, platen/carrier rotation, slurry flow, conditioning sweep profileetc. Advances in CMP equipment technologies have also enabled new possibility such as multi-zone carrier pressure control through APC for within-wafer non-uniformity (WiWNU) reduction. Another widely-adopted approach is to rely on the high-selectivity of slurries to “stop dead” on the final layer of interests (e.g., tungsten in the case of RMG) without creating excessive local topography due to oxide erosion. While all the above approaches prove effective to certain degree, they are, by nature, wafer-level to sub wafer-level processes. As a consequence, it is difficult for them to differentiate between dies locally, for example, and correct the non-uniformity accordingly to the range of a few nanometers. In this contribution, an alternative planarization scheme for RMG is presented to enable nano-scale gate height uniformity control across all dies on 300mm wafers. The new scheme begins with conventional high-selectivity CMP process (pass-1 W-CMP) to remove overburden and polish the gate height down to a few nanometers thicker than the final target, followed by all-die gate height measurement on all wafers. Then the gate height data are fed forward to a GCIB tool, where location-specific process (LSP) takes place to trim the oxide down to a pre-determined target, die by die, through high-energy raster ion beam with high oxide-to-tungsten selectivity. This is followed by a final tungsten touch-up CMP process with high tungsten-to-oxide selectivity to level off the protruded metal patterns and drive the gate height to final target. Applied to SOI-based deep-trench (DT) and FINFET integrated wafers based on 14nm ground rule, the new RMG planarization scheme above demonstrates supreme gate height uniformity. Gate height WiWNU reduces continuously from ~ 2.95% post pass-1 W-CMP to 1.85% post GCIB, and to 1.51% post T/U CMP. The 3sigma of gate height across all dies on 300mm wafers is less than 3nm. The underlying mechanism to achieve nano-scale planarity and uniformity control by this new planarization method will be discussed.

Amorphorized tantalum-nickel binary films for metal gate applications

Amorphous metal gates have the potential to eliminate the work function variation due to grain orientation for poly-crystalline metal gate materials, which is a leading contributor to threshold voltage variation for small transistors. Structural and electrical properties of TaNi alloys using co-sputtering with different compositions and multilayer structures with different thicknesses are investigated in this work. It is found that TaNi films are amorphous for a wide range of compositions as deposited, and the films stay amorphous after annealing at 400 °C in RTA for 1 min and up to at least 700 °C depending on the composition. The amorphous films eventually crystallize into Ni, Ta, and TaNi3 phases at high enough temperature. For multilayer Ta/Ni structures, samples with individual layer thickness of 0.12 nm and 1.2 nm are amorphous as deposited due to intermixing during deposition, and stay amorphous until annealed at 500 °C. The resistivity of the films as-deposited are around 200 μΩ·cm. The work function of the alloy is fixed at close to the Ta work function of 4.6 eV for a wide range of compositions. This is attributed to the segregation of Ta at the metal-oxide interface, which is confirmed by XPS depth profile. Overall, the excellent thermal stability and low resistivity makes this alloy system a promising candidate for eliminating work function variation for gate last applications, as compared to crystalline Ta or TiN gates.

Advanced PVD TiN for Metal Gate Application

High-κ metal gate is widely used for 32nm and beyond to enable scaling down of MOSFET geometry while improving device speed and gate leakage. This structure requires a good work function metal to tune Vt as well as a stable metal barrier to control inter-diffusion and interaction between the multiple metal gate layers. To meet the integration requirements of metal gate, it is very important to choose the proper metal thin film process. Its stability and excellent integration performance make TiN a good option for metal gate application, but the traditional PVD (physical vapor deposition) TiN process still faces issues, such as plasma damage and poor gap-fill capability. RFPVD (radio frequency physical vapor deposition) TiN has been developed for metal gate application. This paper presents studies of the film texture, density, and inter-diffusion base on different metal gate layers. MOSCAP (metal oxide silicon capacitor) tests showed that RF PVD TiN exhibits low Dit and device leakage. To meet the strict gap-fill requirement of the gate-last scheme, physical gap-fill performance of the high-pressure RF TiN process was checked. It achieved more than 60% bottom coverage and minimal sidewall coverage, allowing the electrode gap-fill window to be effectively enlarged.

Investigation of aluminum film properties and microstructure for replacement metal gate application

The fundamental film properties and micro-structures of the different aluminum (Al) metal layers are evaluated to fabricate a replacement metal gate (RMG) device for the high-k metal gate (HKMG) application at 28nm node. A PVD Al fill-in metal deposition process, called one step hot Al (HAL), was found the resistivity increases with increasing the thickness of the Ti wetting layer. The higher pinhole density with the preferred (111) crystal orientation in the HAL layers indicate the film properties with lower reflectivity, higher resistivity and lower removal rate of the Al chemical mechanical polishing (AlCMP). In contrast, the other PVD Al deposition approach, called two steps cold hot Al (CHAL), was identified to possess lower resistivity and higher reflectivity without pinhole structures than the HAL. The smaller grain sizes with the preferred (220) orientation in the CHAL could effectively prevent the formation of pinhole and enhance the removal rate of the AlCMP. The non-uniform with crystallized TiAl3 phase detected in the bottom of the as-deposited HAL and CHAL films could obviously impact the removal rate of the AlCMP. An optimized CHAL fill-in metal deposition process with a larger than 40A Ti wetting layer are needed to simultaneously meet the process requirements of the Al gapfill and AlCMP planarization for achieving a reliable RMG structures.

Chemical Mechanical Polishing of Al-Co Films for Replacement Metal Gate Applications

Further development of a novel cobalt-Al-based metal fill scheme that can be scaled to 11 nm requires the planarization of the metal overfill overburden while also protecting it from corrosion. Very recently, we showed that KMnO4 and sucrose-based aqueous solutions can reduce the ΔEcorr between Al and Co to ∼10 mV. The present work describes the development of the associated silica-based slurry compositions for polishing the Al-Co alloy films. The influence of dodecyl benzene sulfonic acid (DBSA) in tuning the selectivity of the slurry to achieve the desired gate height control and on corrosion currents will also be described.

3D MOSCAP Vehicle for Electrical Characterization of Sidewall Dielectrics for 3D Monolithic Integration

We have developed 3D MOSCAP to characterize sidewall dielectric electrical performance to help gauge quality and reliability of non-planar devices, such as FinFETs. The 3D MOSCAP can be used for process and materials development for high K metal gate, spacer, and liner applications for 3D monolithic integration for future generation devices. In comparison, traditional 2D (planar) MOSCAP is for characterization of dielectrics in the horizontal plane only. This study used different oxides as examples to compare sidewall dielectric quality and electrical performance, and compare with that of oxide on horizontal surface. Data analysis methodology is developed and demonstrated to extract sidewall dielectric properties from measured electrical results.

(Invited) A Study of Dielectric Breakdown Mechanisms in MG/HK MISFETs: From the Viewpoint of TDDB Statistics

The Time Dependent Dielectric Breakdown mechanisms of n/p-FETs having high-k gate dielectrics have been studied through the Weibull distribution. From the thickness dependence of Weibull beta, it is found that the breakdown in n-FETs and p-FETs is mostly determined by the breakdown of high-k layer and interfacial layer (I.L.), respectively. Furthermore, Weibull beta in p-FETs is found to be independent of the injected carrier ratio (Jhole/Jelectron) while those in n-FETs strongly depend on this ratio. Improvement of Weibull beta through the control of the injected carrier ratio together with metal gate application leads to extremely longer lifetime in n-FETs. Improvement of average Tbd through the control of hydrogen concentration in high-k leads to longer life time also in p-FETs.

Tunable Work-Function Engineering of TiC–TiN Compound by Atomic Layer Deposition for Metal Gate Applications

In this paper, we present the impact of the atomic layer deposition of carbon-containing TiN films (TiC–TiN) on the effective work function of metal-oxide-semiconductor devices. By adjusting the deposition temperature of TiC–TiN, the carbon content, which is dependent on the deposition mode, could be altered. Hence, the work function of TiC–TiN as a metal gate material could be tuned. The results revealed that the bonding concentration of Ti–C increases at higher deposition temperatures, whereas the work function of the TiC–TiN metal gate decreases from 5.0 to 4.6 eV. A high work function (5.0 eV) metal gate is suitable for a p-field effect transistor (FET) application and the midgap work function (4.6 eV) is suitable for a fully depleted silicon-on-insulator FET.

Investigation on Molybdenum and Its Conductive Oxides as p-Type Metal Gate Candidates

In this work, we studied molybdenum (Mo) and its conductive oxides for p-type metal gate application. Three compositions of have been investigated. The resistivity of was found to significantly increase with the oxygen incorporation. A clear phase separation of all compositions was observed after high-temperature thermal treatment. The incorporation of oxygen was found to be effective to increase the work function (WF) of Mo. However, after full device integration, a significant WF decrease of was observed, which may be induced during the high-temperature junction activation process. This high-temperature process also led to a significant interfacial silicon oxide layer growth for gated stacks. The equivalent oxide thickness dependent flatband voltage roll-off behavior and gate leakage will also be discussed.

Using Ellipsometry for Assessment of TiN Surface Roughness after Plasma Etch

Titanium nitride (TiN) is widely used in metal gate applications. Exposing TiN to a plasma results in pronounced surface roughness that can be easily characterized by ellipsometry. The ellipsometric angle Δ is proportional to the roughness if the roughness does not exceed . It is possible to plot a “roughness diagram” where a border can be drawn between the smooth and rough etch surfaces depending on the etch conditions. This diagram could be used for gate-etch process optimization. In our case, the roughness could be overcome by increasing HBr content and/or substrate bias during the etching.

Investigation on Molybdenum and Its Conductive Oxides as p-type Metal Gate Candidates

In this work, we studied molybdenum (Mo) and its conductive oxides (MoOx) for p-type metal gate application. Three compositions of MoOx have been investigated in this work. The resistivity of Mo/MoOx was found to significantly increase with increasing oxygen incorporation. Clear phase separation of all MoOx was observed after high temperature thermal treatment. Incorporation of oxygen was found to be effective to increase the work function (WF) of Mo. However, after full integration process, significant WF decrease of MoOx was also observed, which may be induced during the high temperature junction activation process. The interfacial silicon oxide layer growth and the EOT dependent Vfb roll-off behavior will also be discussed.

Band-edge metal gate materials for atomic-layer-deposited HfO 2 for future CMOS technology

In this paper, two different materials are studied for silicon band edge work function. Sc metal gate with thin interface TaN x layer is investigated for n-channel metal-oxide semiconductor (NMOS) metal gate application. The control of TaN x layer thickness is necessary to achieve improved thermal stability and work function (WF) as low as 4.0 electron volts (eV). RuO x also has been demonstrated for p-channel metal-oxide semiconductor (PMOS) application. RuO x WF tends to increase in comparison with elemental Ru metal. This may be due to improved thin film properties like better adhesion and roughness for RuO x . Overall both Sc and RuO x are revealed as candidate materials for future CMOS technology.

Ultralow work function of scandium metal gate with tantalum nitride interface layer for n-channel metal oxide semiconductor application

The authors have investigated n-channel metal oxide semiconductor compatible metal gate with ultralow work function using tantalum nitride (TaNx)/scandium(Sc) stack layer. By adjusting the deposition condition, the effective work function as low as 4.0eV with improved thermal stability can be obtained. Without TaNx layer, work function of pure Sc gate on HfO2 was about 4.2eV and show thermal instability at high temperature which can be explained by reaction between Sc and HfO2. The authors found that control of TaNx layer is the critical process to maintain thermal stability and work function. The TaNx∕Sc stack process shows promise for future high-k metal gate applications.

Chemical vapor deposition of tantalum nitride films for metal gate application using TBTDET and novel single-source MOCVD precursors

In this paper, physical and electrical properties of TaN films used as metal electrodes in MOS structures are discussed. TaN films were deposited by MOCVD from commercial TBTDET and two novel mixed amido/imido/guanidinato and mixed amido/imido/hydrazido precursors. It will be shown that morphology (only films deposited from the guanidinato compound above 750 °C showed cubic TaN phase while all other films were amorphous) and O content (5 at.% and 25 at.% in case of guanidinato and in case of TBTDET precursor, respectively) do not necessary predetermine resistivity. Lowest resistivity (230 μΩ cm) was obtained for TBTDET. Evaluated values of metal work function are 4.4–4.6 eV (TBTDET) and 3.9 eV (guanidinato compound). Films deposited from the hydrazido compound reveal bad electrical properties (e.g., metal layers behave dielectric-like).

Electrical and Physical Analysis of MoTa Alloy for Gate Electrode Applications

This article presents as a potential candidate for dual metal complementary metal oxide semiconductor (CMOS) applications. The electrical characterization results of alloy indicates that the effective work function can be controlled to around on and is suitable for n-type MOS gate electrode application. The alloy forms a solid solution instead of an intermetallic compound. We report that the solid solution can achieve low work function values and is stable up to . X-ray diffraction results indicated only a single alloy phase. X-ray photoelectron spectroscopy analysis confirmed that no compound bonding formed within the alloy. Moreover, from Auger electron spectroscopy and Rutherford backscattering spectroscopy analysis, was found to be stable on under high-temperature anneals and no metal diffusion into substrate Si channel was detected. This indicates that is a good candidate for CMOS metal gate applications.

Atomic vapor deposition of Ru and RuO 2 thin film layers for electrode applications

Ru and RuO 2 thin films for advanced metal gate applications were deposited on 200 mm SiO 2/Si substrate by the novel deposition technique atomic vapor deposition (AVD™). AVD™ was carried out in an Aixtron Tricent™ system using liquid delivery of the Ru precursor. The creation of Ru- and RuO 2-films is controlled by varying the O 2 flow and deposition temperature. Ru layers with a near bulk resistivity of 10 μΩ cm and a uniformity of ∼2% for 20 nm film thickness were obtained at 450 °C deposition temperature. The smooth Ru layers have a thickness uniformity of about 2% and a roughness <1 nm. XRD measurements exhibit multi-crystalline Ru-films with a preferable orientation along the (0 0 2) plane. Adding O 2-flow RuO 2 layers were grown at 380 °C. RuO 2-films with a resistivity of about 80 μΩ cm and <2% uniformity were achieved for 30 nm thick films. The roughness of the RuO 2 layers is about 2 nm for 10–20 nm thickness. No Ru-crystallites could be detected in the RuO 2 layers by XRD. The thermal stability of the grown Ru and RuO 2 films was investigated by rapid thermal annealing in O 2 and N 2 atmosphere. Ru films were found to be stable in N 2 up to 900 °C and up to 500 °C in O 2. RuO 2-layers have been shown to be stable in O 2 up to at least 600 °C.