Maximum Power-added Efficiency Research Articles

11–17 GHz Reconfigurable Stacked Power Amplifier Using Matched Slant Microstrip Line for Ku Band Application

In this paper, a reconfigurable stacked CMOS power amplifier using matched microstrip slant line for Ku-band application is proposed. This work is mainly focused on a matching component which is microstrip line and it is slanted at 45°. This component is applied in stacked power amplifiers which provide a higher output power and enhanced power added efficiency (PAE), improved impedance matching and wide impedance bandwidth. Two, three and four stacked power amplifiers with matched microstrip slant lines are designed, analyzed and compared. First demonstration uses a single microstrip slant line that covers a frequency range of operation from 7 to 15.9 GHz with impedance bandwidth of 8.9 GHz. This impedance bandwidth can be enhanced using proposed two or more stacks of microstrip slant lines and exhibits greater than 20 GHz impedance bandwidth with reconfigure band of operation. Two, three and four stacked power amplifiers are designed and simulated in the advanced design system using 45 nm predictive technology model process. As per the results of PAs, effective four stacked power amplifier design achieves maximum PAE of 57 % while a saturated output power of 20 dBm. The forward gain of 17.5 dB is obtained within frequency range of 11---17 GHz.

A harmonic-suppressed high-efficiency class-F power amplifier with Elliptic-Function low-pass filter

In this paper, a novel method is developed in order to design a harmonic control circuit block using a compact microstrip low-pass filter (LPF) for a P-HEMT class-F PA. The design procedure is performed using Harmonic-Balance analysis. The key benefit is a novel compact defected Elliptic-Function resonator to design a LPF, which has a wide rejection band. The advantages of the presented method are the attenuation of nth harmonics in AM-AM distortion, high power added-efficiency (PAE) and more linearity in comparison with a conventional class-F PA. The experiment is carried out at 1.8GHz and shows a maximum PAE about 77% with 40dBm output power.

Fully-integrated bias control feed-back loop for efficiency enhancement of mmWave CMOS power amplifier

A single-stage mmWave class-A CMOS power amplifier (PA) is fabricated in a BiCMOS 55 nm technology. In order to improve the power added efficiency (PAE) behavior of the PA, a bias-control feedback loop is fully implemented on-chip in order to dynamically adjust the DC bias current of the PA according to RF envelope power level. A tunable envelope detector is connected directly at the output of the amplifier in order to track the envelope variations of the output signal. Under constant bias conditions, the PA has a power gain (Gp) of 4.2 dB, a maximum PAE of 14 %, and an output compression point of around 7.5 dBm while driving 25 mA under 1.2 V supply voltage. In adaptive bias mode, the mean value of the DC current is reduced down to 20.8 mA, while holding the same Gp, leading to a good enhancement of the PAE over the linear input dynamic range of the PA. Simulations and measurements with a modulated 16-QAM 700 MHz input signal show that the applied technique improves the average PAE and DC power consumption by 17 % (relative to is nominal value) without significant degradation of the signal quality. For our best knowledge, the measurements with modulated signal are the first to be done on a dynamically biased mmWave PA.

Characteristics of GaAs Power MESFETs with Double Silicon Ion Implantations for Wireless Communication Applications

GaAs power metal-semiconductor field-effect transistors (MESFETs) were fabricated using direct double silicon (Si) ion implantation technology for wireless communication applications. A 150-µm MESFET had a saturation drain current of 238 mA/mm after Si3N4passivation. A 15-mm MESFET, when measured under a class-AB condition with a biased drain voltage of 3.4 V and a quiescent drain current of 600 mA, delivered a maximum output power (Pout) of 31.1 dBm and a maximum power-added efficiency (PAE) of 58.0% at a frequency of 1.88 GHz. The MESFET exhibited aPoutof 29.2 dBm with a PAE of 45.0% at the 1-dB gain compression point. The MESFET, when measured under a deep class-B condition with a biased drain voltage of 4.7 V and a quiescent drain current of 50 mA, achieved a maximumPoutof 33.1 dBm and a maximum PAE of 55.9% at 1.88 GHz. The MESFET operating at 4.7 V and 1.88 GHz exhibited aP1dBof 31.8 dBm and an associated PAE of 47.1% at the 1-dB gain compression point. When tested by IS-95 code-division multiple access (CDMA) standard signals and biased at 4.7 V under the deep class-B condition, the MESFET with aPoutof 28 dBm demonstrated an adjacent channel power rejection (ACPR) of –31.2 dBc at +1.25 MHz apart from the 1.88 GHz center frequency and –45.7 dBc at +2.25 MHz.

A Broadband Integrated Class-J Power Amplifier in GaAs pHEMT Technology

This paper presents a design methodology for class-J monolithic microwave integrated circuit (MMIC) power amplifiers (PAs). Theoretical derivations of optimum load impedances, output power, efficiency, and maximum bandwidth are described in presence of nonlinear drain–source resistance of transistors $(R_{DS})$ . A procedure is developed for ideal transistor sizing where transistors are concurrently stabilized and sized to achieve the maximum power-added efficiency (PAE). A 3.5–7 GHz, 0.5-W class-J PA is implemented in a $\text {0.1-}\mu \text {m}$ AlGaAs–InGaAs pHEMT technology to check the accuracy of the proposed approach. With chip dimensions of $1.57 \,\, \times \text {1.29 mm}^{2}$ , the PA achieves 56% average PAE over the frequency band while maintaining an average 11-dB small-signal gain.

First Power Performance Demonstration of Flexible AlGaN/GaN High Electron Mobility Transistor

This letter reports on the first demonstration of microwave power performance at 10 GHz on flexible AlGaN/GaN high-electron-mobility transistor (HEMT). A maximum dc current density of 620 mA/mm at $\text{V}_{\mathrm {GS}} = 0$ V and a peak extrinsic transconductance of 293 mS/mm are obtained for a $2\times 50 \times 0.1~\mu \text{m}^{2}$ flexible device. At $\text{V}_{\mathrm {DS}} = 5$ V, a continuous-wave saturation output power density of 0.42 W/mm is achieved at 10 GHz, and associated with a maximum power-added efficiency of 29.8% and a linear power gain of 15.8 dB. The device exhibits an intrinsic current gain cutoff frequency $F_{T}$ of 38 GHz and a maximum oscillation frequency $\text{F}_{\mathrm {MAX}}$ of 75 GHz. This result demonstrates the capability of flexible GaN-based HEMT for the development of applications requiring mechanical flexibility, high frequency operation, as well as high power performance.

차량 추돌 방지 레이더용 24-GHz 전력 증폭기 설계

ABSTRACT In this paper, we propose 24-GHz CMOS radio frequency (RF) power amplifier for short-range automotive collision avoidance radars. This circuit contains common source stage with inter-stages conjugate matching circuit as a class-A mode amplifier. The proposed circuit is designed using TSMC 0.13-µm mixed signal/RF CMOS process (     =120/140GHz). It operates at the supply voltage of 2V, and it is designed to have high power gain, low insertion loss and low noise figure in the low supply voltage. To reduce total chip area, the circuit used transmission lines instead of the bulky real inductor. The designed CMOS power amplifier showed the smallest chip size of 0.1mm 2 , the lowest power consumption of 40mW, the highest power gain of 26.5dB, the highest saturated output power of 19.2dBm and the highest maximum power-added efficiency of 17.2% as compared to recently reported results. 키워드 : 24-GHz, 차량 추돌 방지, CMOS 전력증폭기, 전송선 Key word : 24GHz, automotive collision avoidance, CMOS power amplifier, transmission linesJournal of the Korea Institute of Information andCommunication Engineering

High‐efficiency CMOS push‐pull power amplifier with multilayer center‐tapped transformer

This paper describes the design of a push‐pull power amplifier (PA) with a center‐tapped transformer for transmitter applications on the 5.2‐GHz band using 0.18μm CMOS technology. The type of the proposed PA is based on a double‐ended push–pull (DEPP) configuration. DEPP has a simple construction with only transistors and transformers. The PA has reverse‐phased cascode‐connected transistors. The proposed transformer has a multilayer structure and was designed using electromagnetic field simulation. To achieve high power added efficiency (PAE), we assumed the optimized output impedance technique with a tunable impedance antenna. The PA has 13.2 dB linearity gain, 14.9 dBm 1‐dB compression point (P1dB), and 27.4% maximum PAE. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

A wideband CMOS power amplifier with 23.3 dB S21, 10.6 dBm PSAT and 12.3 % PAE for 60 GHz WPAN and 77 GHz automobile radar systems

A wideband power amplifier (PA) for 60 and 77 GHz direct-conversion transceiver using standard 90 nm CMOS technology is reported. The PA comprises a cascode input stage with a wideband T-type input-matching network and inductive interconnection and load, followed by a common-source (CS) gain stage and a CS output stage. To increase the saturated output power (PSAT) and power-added efficiency (PAE), the output stage adopts a two-way power dividing and combining architecture. Instead of the area-consumed Wilkinson power divider and combiner, miniature low-loss transmission-line inductors are used at the input and output terminals of each of the output stages for wideband input and output impedance matching to 100 Ω. This in turn results in further PSAT and PAE enhancement. The PA consumes 92.2 mW and achieves maximum power gain (S21) of 23.3 dB at 56 GHz, and S21 of 21.7 and 14 dB, respectively, at 60 and 77 GHz. In addition, the PA achieves excellent saturated output power (PSAT) of 10.6 dBm and maximum power added efficiency (PAE) of 12.3 % at 60 GHz. At 77 GHz, the PA achieves excellent PSAT of 10.4 dBm and maximum PAE of 6 %. These results demonstrate the proposed wideband PA architecture is very promising for 60 GHz wireless personal local network and 77 GHz automobile radar systems.

A Broadband 4.5–15.5-GHz SiGe Power Amplifier With 25.5-dBm Peak Saturated Output Power and 28.7% Maximum PAE

This paper presents the design of a broadband power amplifier (PA) in 130-nm SiGe BiCMOS technology. First, a single-stage broadband single-cell PA covering the 4.5–18-GHz frequency band is introduced. In this frequency range, this single cell achieves a measured gain, saturated output power $({ P}_{\rm sat})$ , output 1-dB compression point $({ P}_{1{\rm dB}})$ , and power-added efficiency (PAE) in the range from 12.8 to 15.7 dB, 18.8 to 23.7 dBm, 16.7 to 19.5 dBm, and 11.4 to 31.9%, respectively. Its peak saturated output power and maximum PAE are both obtained at 8.5 GHz. Second, to increase the output power, a PA consisting of two parallel broadband cells with a power combination is presented. This PA operates in the 4.5–15.5-GHz frequency range with measured gain, ${ P}_{\rm sat}, { P}_{1{\rm dB}}$ , and PAE in the range from 11 to 16.6 dB, 21.3 to 25.5 dBm, 18.7 to 21.7 dBm, and 11.9 to 28.7%, respectively. It achieves its peak saturated output power of 25.5 dBm at 8.5 GHz and its maximum PAE of 28.7% with an associated output power of 23.6 dBm at 6.5 GHz. Each of those two PAs achieves better performances than the state-of-the-art in broadband SiGe technology when comparing the output power level and efficiency.

A New Distributed Parameter Broadband Matching Method for Power Amplifier via Real Frequency Technique

A general matching method is presented in this paper for broadband power amplifier (PA) design. A novel cost function is proposed for the real frequency technique (RFT), which could straightforwardly describe PA optimal impedance along with frequency change. The new function is also developed to design a broadband transformer for the PA output matching network (MN). Based on Richard transformation, a commensurate transmission line is deployed so that the PA matching could be convenient expressed by a real positive function. More important is that the function could be directly implemented with a distributed MN through synthesis theory. Therefore, this method is practical for computer-aided design and has less calculation amount with new function for the RFT. To verify the method, a step-by-step design of a broadband PA is given. For large signals, power gain is 14.2–16.8 dB across 0.9–2.8 GHz, while output power is around 39.5 dBm. The maximum power-added efficiency is from 52.2% to 85.1%.

A Miniature Broadband Doherty Power Amplifier With a Series-Connected Load

A microwave Doherty power amplifier (DPA) consists of a carrier amplifier (CA), a peaking amplifier (PA), and an impedance inverting network. In this paper, a novel DPA topology with neither the impedance inverting network nor offset lines is proposed. This topology enables the enhancement of amplifier bandwidth and achieves a more compact amplifier size. To remove the impedance inverting network and to realize high efficiency at large back-off power level, the output-matching network of the CA is designed to realize high performance both at a low signal power level in the off-state of the PA and at the saturated signal power level. A 1.9-GHz series-connected load Doherty power amplifier without an impedance inverting network is designed and fabricated using GaN HEMTs. The amplifier achieves a power-added efficiency (PAE) of 50% under a 6-dB output back-off from a 34-dBm saturated output power with a PAE of 59%. A maximum PAE higher than 44% is obtained over a frequency range of 1.63-1.98 GHz.

A 60 GHz power amplifier with Psat of 13.1 dBm, PAE of 11 % and excellent matching in 90 nm CMOS for 60 GHz short-range communication systems

A 60 GHz power amplifier (PA) for direct-conversion transceiver using standard 90 nm CMOS technology is reported. The PA comprises a cascode input stage with inductive interconnection and load, followed by a common-source gain stage and a common-source output stage with source-degeneration. To increase the saturated output power (PSAT) and power-added efficiency (PAE), the output stage adopts a two-way power dividing and combining architecture. Instead of the area-consumed Wilkinson power divider and combiner, miniature low-loss transmission-line inductors are used at the input and output terminals of each of the output stages for wideband input and output impedance matching to 100 Ω. This in turn results in further PSAT and PAE enhancement. The PA consumes 128 mW and achieves power gain (S21) of 11.5 ± 0.4 dB, input-port input reflection coefficient (S11) of ?15.7 to ?17.9 dB, and output-port input reflection coefficient (S22) of ?15.5 to ?30.8 dB for frequencies of 57---64 GHz. In addition, the PA achieves output 1-dB compression point (OP1dB) of 7.5 dBm, PSAT of 13.1 dBm and maximum PAE of 11 % at 60 GHz, one of the best PAE results ever reported for a 60 GHz CMOS PA. These results demonstrate the proposed PA architecture is very promising for 60-GHz short-range communication system applications.

A Peak-Search Algorithm for Load–Pull Optimization of Power-Added Efficiency and Adjacent-Channel Power Ratio

Power amplifiers in modern wireless systems must meet increasingly stringent spectral constraints while still operating with high power efficiency. A new peak-search algorithm is demonstrated to find the Pareto optimum of power-added efficiency (PAE) while producing an adjacent channel power ratio (ACPR) value under a specified maximum. A peak-search is first performed for the maximum PAE, and then a small-step steepest descent walk in the ACPR is taken from the PAE maximum toward the ACPR minimum until ACPR requirements are met. This approach reasonably approximates the Pareto optimum for the device. Simulation and measurement data are presented for searches from multiple starting points, and good correspondence is obtained for the Pareto optimum reflection coefficient, as well as the optimum PAE and ACPR values. This measurement-based algorithm is expected to find useful application in real-time adaptive radio and radar transmitters, as well as in bench-top measurements for amplifier design.

An ultrawideband CMOS power amplifier using two-stage distributed matching techniques

An ultrawideband CMOS power amplifier (PA) with high efficiency, high P1dB, and flat small signal gain is proposed. The CMOS PA uses the distributed amplifier concept to extend the operating bandwidth from 3.1 to 10.6 GHz, and incorporates the active load modulation technique to improve the power-added efficiency (PAE). The active load modulation is realized with two cascode power stages using two different bias classes (class-AB and class-B) to increase the PAE. The experimental results show that the output P1dB is 17.5 dBm with the maximum PAE of 24.6% at 4 GHz. The measured small signal gain is 8 ± 0.3 dB from 3.1 to 10.6 GHz. The proposed PA is implemented in a 0.13-μm CMOS process, and the chip area is 0.64 mm2 including pads. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:1757–1759, 2014

New Technique for Synthesizing Concurrent Dual-Band Impedance-Matching Filtering Networks and ${\hbox{0.18-}}\mu{\hbox {m}}$ SiGe BiCMOS 25.5/37-GHz Concurrent Dual-Band Power Amplifier

New technique for synthesizing concurrent dual-band impedance-matching filtering networks is presented. The technique enables the design of concurrent dual-band impedance-matching filtering networks that provide not only simultaneous matching of two arbitrary loads to two arbitrary sources at two different frequencies, but also dual-bandpass filtering response capable of suppressing unwanted signals like the harmonics and inter-modulation products in nonlinear circuits, such as power amplifiers (PAs). A new 0.18-μm SiGe BiCMOS concurrent dual-band PA was designed based on the developed dual-band matching filtering technique around 25.5 and 37 GHz, which works in the concurrent dual-band mode (25.5 and 37 GHz), as well as single-band mode (25.5 or 37 GHz). The measured results show that, in the single-band mode, the dual-band PA exhibits gain of 21.4 and 17 dB, maximum output power of 16 and 13 dBm, and maximum power-added efficiency (PAE) of 10.6% and 4.9% at 25.5 and 37 GHz, respectively. In the dual-band mode, the maximum output power is 13 and 9.5 dBm at 25.5 and 37 GHz, respectively, and the total maximum PAE is 7.1%. The designed concurrent dual-band PA has a chip size of 1.3×0.68 mm2 and consumes a dc current of 120 mA from a 3-V supply voltage.

A High‐Voltage Driving 60‐GHz Power Amplifier with Psat of 13 dBm and PAE of 9.1% in 90‐nm CMOS for IEEE 802.11ad Communication Systems

ABSTRACTA high‐voltage (3 V) driving 60‐GHz power amplifier (PA) for direct‐conversion transceiver using standard 90 nm CMOS technology is reported. The PA comprises two cascode stages with inductive load and low‐impedance interstage matching, followed by a common‐source output stage. To increase the saturated output power (Psat) and power‐added efficiency (PAE), the output stage adopts a two‐way power dividing and combining architecture. Instead of the area‐consumed Wilkinson power divider and combiner, miniature low‐loss LC power divider and combiner (IL = 0.536 dB @60 GHz) are used. This in turn results in further Psat and PAE enhancement. The PA consumes 176.2 mW and achieves power gain (S21) of 17.9 ± 3.7 dB, input‐port input reflection coefficient (S11) of −5.8 to −7.3 dB, output‐port input reflection coefficient (S22) of −10.4 to −26.3 dB, and reverse isolation (S12) of −56.4 to −81.7 dB for frequencies 50–60 GHz. In addition, for frequencies 50–60 GHz, the PA achieves output 1‐dB compression point (OP1dB) of 6.6–7.8 dBm, Psat of 10.6–13 dBm and maximum PAE of 9.1%, one of the best PAE results ever reported for a 60 GHz CMOS PA. These results demonstrate the proposed PA architecture is very promising for 60‐GHz short‐range communication system applications. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2033–2039, 2013

Analysis and Design of Stacked-FET Millimeter-Wave Power Amplifiers

Stacked field-effect transistor (FET) CMOS millimeter-wave power amplfiers (PAs) are studied with a focus on design of appropriate complex impedances between the transistors. The stacking of multiple FETs allows increasing the supply voltage, which, in turn, allows higher output power and a broader bandwidth output matching network. Different matching techniques for the intermediate nodes are analyzed and used in two-, three-, and four-stack single-stage $Q$ -band CMOS PAs. A four-stack amplifier design achieves a saturated output power greater than 21 dBm while achieving a maximum power-added efficiency (PAE) greater than 20% from 38 to 47 GHz. The effectiveness of an inductive tuning technique is demonstrated in measurement, improving the PAE from 26% to 32% in a two-stack PA design. The input and output matching networks are designed using on-chip shielded coplanar waveguide transmission lines, as well as metal finger capacitors. The amplifiers were implemented in a 45-nm CMOS silicon-on-insulator process. Each of the amplifiers occupies an area of 600 $\mu$ m $\,\times\,$ 500 $\mu$ m including pads.

A high-performance CMOS power amplifier for 60 GHz short-range communication systems

A 60 GHz power amplifier for direct-conversion transceiver using standard 90 nm CMOS technology is reported.The power amplifier comprises three cascaded common-source stages with inductive load and inter-stage matching. To increase the saturated output power (Psat) and power-added efficiency (PAE), the output stage adopts a two-way power dividing and combining architecture. Instead of the area-consumed Wilkinson power divider and combiner, miniature low-loss LC power divider and combiner are used. This in turn results in further Psat and PAE enhancement. Over the 57 ∼ 64 GHz frequency band of interest, the power amplifier consumes 44.4 mW and achieves power gain (S21) of 12.04 ± 1 dB, input-port input return loss (S11) of −6 to −9.4 dB, output-port input return loss (S22) of −10.4 to −26.4 dB, and reverse isolation (S12) of −29.2 to −30.6 dB. At 60 GHz, the power amplifier achieves Psat of 11.4 mW and maximum PAE of 15.8%. To the authors' knowledge, this is the best PAE ever reported for a 60 GHz CMOS power amplifier. In addition, the measured output 1-dB compression point (OP1 dB) is 6 dBm at 60 GHz. These results demonstrate that the proposed power amplifier architecture is very promising for 60-GHz short-range communication systems. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:1155–1160, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27522

A Broadband Injection-Locking Class-E Power Amplifier

This paper presents a fully integrated two-stage injection-locking class-E power amplifier (PA) using a GaAs 0.5-μm enhancement- and depletion-mode pseudomorphic high-electron mobility transistor (E/D-mode PHEMT) process. The injection-locking concept is used in this design, and the PA works as an oscillator whose output voltage is tuned at the input frequency. The proposed PA achieves high power-added efficiency (PAE) and high power gain. An autonomous circuit is also employed for the stability analysis, and the design procedure is summarized for the circuit implementation. By employing this design technique, the proposed injection-locking class-E PA under continuous-wave signal achieves a peak PAE of 59% at an output power of 26.6 dBm from a 6-V dc supply voltage. With a Gaussian minimum-shift keying (GMSK) modulation input signal at 3.5 GHz, the measured maximum PAE is 57% at an output power of 26.7 dBm. The measured error vector magnitude is within 2.2% over all of the output power level, and the adjacent channel power ratio is better than - 40 dBc. Under a 64-QAM modulation signal with class-AB operation, the proposed PA achieves a peak PAE of 55% with an output power of 27 dBm.