A 60 GHz power amplifier with Psat of 13.1 dBm, PAE of 11 % and excellent matching in 90 nm CMOS for 60 GHz short-range communication systems

Abstract

A 60 GHz power amplifier (PA) for direct-conversion transceiver using standard 90 nm CMOS technology is reported. The PA comprises a cascode input stage with inductive interconnection and load, followed by a common-source gain stage and a common-source output stage with source-degeneration. To increase the saturated output power (PSAT) and power-added efficiency (PAE), the output stage adopts a two-way power dividing and combining architecture. Instead of the area-consumed Wilkinson power divider and combiner, miniature low-loss transmission-line inductors are used at the input and output terminals of each of the output stages for wideband input and output impedance matching to 100 Ω. This in turn results in further PSAT and PAE enhancement. The PA consumes 128 mW and achieves power gain (S21) of 11.5 ± 0.4 dB, input-port input reflection coefficient (S11) of ?15.7 to ?17.9 dB, and output-port input reflection coefficient (S22) of ?15.5 to ?30.8 dB for frequencies of 57---64 GHz. In addition, the PA achieves output 1-dB compression point (OP1dB) of 7.5 dBm, PSAT of 13.1 dBm and maximum PAE of 11 % at 60 GHz, one of the best PAE results ever reported for a 60 GHz CMOS PA. These results demonstrate the proposed PA architecture is very promising for 60-GHz short-range communication system applications.