A high-performance CMOS power amplifier for 60 GHz short-range communication systems

Abstract

A 60 GHz power amplifier for direct-conversion transceiver using standard 90 nm CMOS technology is reported.The power amplifier comprises three cascaded common-source stages with inductive load and inter-stage matching. To increase the saturated output power (Psat) and power-added efficiency (PAE), the output stage adopts a two-way power dividing and combining architecture. Instead of the area-consumed Wilkinson power divider and combiner, miniature low-loss LC power divider and combiner are used. This in turn results in further Psat and PAE enhancement. Over the 57 ∼ 64 GHz frequency band of interest, the power amplifier consumes 44.4 mW and achieves power gain (S21) of 12.04 ± 1 dB, input-port input return loss (S11) of −6 to −9.4 dB, output-port input return loss (S22) of −10.4 to −26.4 dB, and reverse isolation (S12) of −29.2 to −30.6 dB. At 60 GHz, the power amplifier achieves Psat of 11.4 mW and maximum PAE of 15.8%. To the authors' knowledge, this is the best PAE ever reported for a 60 GHz CMOS power amplifier. In addition, the measured output 1-dB compression point (OP1 dB) is 6 dBm at 60 GHz. These results demonstrate that the proposed power amplifier architecture is very promising for 60-GHz short-range communication systems. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:1155–1160, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27522