A High‐Voltage Driving 60‐GHz Power Amplifier with Psat of 13 dBm and PAE of 9.1% in 90‐nm CMOS for IEEE 802.11ad Communication Systems

Abstract

ABSTRACTA high‐voltage (3 V) driving 60‐GHz power amplifier (PA) for direct‐conversion transceiver using standard 90 nm CMOS technology is reported. The PA comprises two cascode stages with inductive load and low‐impedance interstage matching, followed by a common‐source output stage. To increase the saturated output power (Psat) and power‐added efficiency (PAE), the output stage adopts a two‐way power dividing and combining architecture. Instead of the area‐consumed Wilkinson power divider and combiner, miniature low‐loss LC power divider and combiner (IL = 0.536 dB @60 GHz) are used. This in turn results in further Psat and PAE enhancement. The PA consumes 176.2 mW and achieves power gain (S21) of 17.9 ± 3.7 dB, input‐port input reflection coefficient (S11) of −5.8 to −7.3 dB, output‐port input reflection coefficient (S22) of −10.4 to −26.3 dB, and reverse isolation (S12) of −56.4 to −81.7 dB for frequencies 50–60 GHz. In addition, for frequencies 50–60 GHz, the PA achieves output 1‐dB compression point (OP1dB) of 6.6–7.8 dBm, Psat of 10.6–13 dBm and maximum PAE of 9.1%, one of the best PAE results ever reported for a 60 GHz CMOS PA. These results demonstrate the proposed PA architecture is very promising for 60‐GHz short‐range communication system applications. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2033–2039, 2013