LSI Circuits Research Articles

Design for test using partial parallel scan

Traditional scan design techniques such as level-sensitive scan design, scan path, and random-access scan suffer from the drawback that the extra test application effort (which includes both time and memory) required is directly proportional to the number of latches and can become quite significant. A scan design technique termed partial parallel scan which reduces test application effort by one to two orders of magnitude is presented. Theoretical and practical aspects of the design method are discussed. The practical use of the partial parallel scan technique has been demonstrated with an LSI circuit and a VLSI circuit designed using silicon compiler tools. >

High-performance CMOS/SOS circuits in SPEAR material

The application of a submicrometer CMOS/SOS process technology in solid-phase epitaxy and regrowth (SPEAR) material to the fabrication of submicrometer devices and LSI circuits is described. Transistors consistently showed relatively high mobilities and relatively low leakage currents, with threshold voltages near designed values. Inverter propagation delays for an 0.6- mu m ring oscillator measured 85 ps at 2 V and 41 ps at 8 V. Three high-speed LSI circuits were also designed and fabricated using a standard cell approach. Maximum clock frequencies for the 16-b universal shift register, the 8-b multiplexer/demultiplexer, and the variable modulus 10/11 prescaler, fabricated with 1- mu m gate lengths, were 125, 158, and 330 MHz, respectively.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

LED array modules by new technology microbump bonding method

An LED array module was developed by using the microbump bonding method by which the electrodes of LSI chips and circuit substrate are press-bonded by utilizing the shrinkage stress produced in a light setting insulating resin. The LED array module has a resolution of 400 DPI, and is constructed by face-down mounting of 54 each of the LED chips and driver LSIs on a glass substrate. These LED chips, having an electrode pitch of 63.5 mu m, are disposed on the glass substrate at a pitch of 10 mu m. A dedicated bonder was developed for this assembling work. A report on the LED array module assembling process and the construction of a bonder is presented. >

低温ＣＭＯＳコンピュータ

Low temperature operation of MOS devices improves performance of LSI circuits because of the increase of carrier mobility, steep subthreshold slopes, elimination of latch-up, decrease of electrical resistance and improved noise behavior. A supercomputer using CMOS circuit technology cooled at liquid-nitrogen temperatures operates at double the speed of the circuit chips as compared to room-temperature operation. A further improvement of the speed in CMOS chips will be possible by optimizing the device design.

A 1.5 Gbit/s GaAs four-channel selector LSI with monolithically integrated newly structured GaAs ohmic contact MSM photodetector and laser driver

A monolithic integrated 1.5 Gb/s high-speed four-channel optoelectronic integrated circuit (OEIC) selector GaAs LSI circuit is discussed. This LSI circuit incorporates photodetectors, preamplifiers, a selector, a decision circuit, and a high-speed laser driver. To achieve high efficiency, a AuGe/Ni-GaAs structured ohmic contact metal-semiconductor-metal (OC-MSM) is used for the interdigitated structural photodetector. With this OC-MSM structure, photocurrent is approximately twice as effective as with the conventional Schottky contact MSM structure. The new LSI has a maximum operating speed of 1.5 Gb/s and exhibits low power dissipation of 927 mW. >

A 10-bit 20-MHz two-step parallel A/D converter with internal S/H

A 10-bit 20-MHz A/D converter for high-quality video systems such as high-definition television, video tape recorders for business use, and digital video cameras is described. This LSI circuit uses a standard two-step parallel architecture, includes automatic gain adjustment and digital two-bit error correction, and has a sample-and-hold circuit on the chip. It is fabricated by a 4.5-GHz f/sub T/. 3- mu m-rule standard bipolar technology. Its die size is 25 mm/sup 2/, and its power consumption is 900 mW, which is about half of the lowest values reported to date. The converter can digitize video signals of up to 8.5 MHz at a conversion frequency of 20 MHz. The error in differential gain is 0.5 percent, and the error in differential phase is 0.5 degrees .< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

MBE as a production technology for HEMT LSIs

Molecular beam epitaxy (MBE) is widely used to produce high quality epitaxial layers for advanced heterostructure devices. High electron mobility transistors (HEMTs) based on selectively-doped AlGaAs/GaAs heterojunction structures are one of the most successful applications of MBE. This paper reviews MBE techniques developed in our laboratories for HEMT LSI fabrication. To meet material requirements for submicron-gate AlGaAs/GaAs HEMT LSIs, we designed a multiwafer MBE system that enables good uniformity and high throughput. Epitaxial growth is done simultaneously on three 3-inch wafers mounted in a 7.5-inch holder. The variations of layer thickness and carrier concentration over the holder area were less than ±1%. One-touch substrate mounting without indium solder was developed for the t.5-inch holder. In-situ monitoring of growth rates by RHEED instensity oscillation with an automated growth system was introduced to control epitaxial parameters precisely. The density of oval defects due to Ga sources was stably controlled to less than 10 cm -2 and carrier depletion at the substrate-epitaxial layer interface was significantly reduced. These excellent material characteristics make it possible to develop high-performance HEMT logic and memory LSI circuits.

The development of heterojunction integrated injection logic

The development of heterojunction integrated injection logic (HI/sup 2/L) since 1982 is described. The baseline process that uses AlGaAs/GaAs emitter-down HBTs (heterojunction bipolar transistors) as the switching element is presented. Two sets of design rules, one using a 7.0- mu m collector and 8.0- mu m metal pitch and another using a 5.0- mu m collector and 5.0- mu m metal pitch, have been developed for the pilot line circuit fabrication. Typical propagation delays obtained for a fan-out=4 HI/sup 2/L gate using the 7.0- and 5.0- mu m collector processes are 250 and 150 ps, respectively, at a power dissipation of 5 mW per gate. LSI and VLSI circuits as complex as 4 K-gate arrays and 32-bit MIPS microprocessors have been fabricated successfully using the HI/sup 2/L technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A new single chip LSI for an NTSC CTV signal processing

A novel single-chip LSI circuit for National Television System Committee color TV (NTSC CTV) signal processing is described. The circuit covers the entire range of TV chassis. The number of external components and PCB (printed circuit board) area can be reduced to approximately 60% of those for a conventional set. The circuit will contribute to the upgrading of standard TV chassis by saving PCB area and increasing the reliability of sets. The circuit integrates 3980 linear elements, a 1200-pF capacitor, and 590 gates on a 5.1*4.5 mm/sup 2/ chip with a shrink 54-pin dual-in-line package (DIP). >

A 200-MHz 16-bit super high-speed signal processor (SSSP) LSI

A 200-MHz 16-b BiCMOS super high-speed signal processing (SSSP) circuit has been developed for high-speed digital signal processor (DSP) LSIs. In order to produce extremely fast LSI circuits, several novel techniques have been combined for integration of the SSSP. They include a redundant binary convolver architecture, a double-stage pipelined convolver architecture, and submicrometer BiCMOS drivers with large capacitive load drivability. The SSSP performs 200-MHz addition. The chip, which was fabricated with 0.8- mu m BiCMOS and triple-layer metallization technology, has an area of 5.87 mm*5.74 mm and contains 20150 transistors. It operates at a clock frequency of 200 MHz with a single 5-V power supply and typically consumes 800 mW. >

ジョセフソンコンピュータの現状

Recent progress in a Josephson computer technology is reviewed. A Josephson computer is very attractive because Josephson digital circuits have the potential for realizing LSI circuits with extremely high performance in both circuit speed and power dissipation. Recently, various Josephson LSIs, such as processors and memories, have been made successfully with Nb or NbN junctions, particularly in Japan. These junctions exhibit high reliability for thermal cycling and long term storage, and have a good uniformity of the Josephson tunnelling current due to the tri-layer junction sandwich process. On the basis of such progress in Josephson IC technology, research, on Josephson computers in which Josephson memories are installed with a processor, is now under way.

A self-aligned gate III-V heterostructure FET process for ultrahigh-speed digital and mixed analog/digital LSI/VLSI circuits

A planar ion-implanted self-aligned gate process for the fabrication of high-speed digital and mixed analog/digital LSI/VLSI integrated circuits is reported. A 4-b analog-to-digital converter, a 2500-gate 8*8 multiplier/accumulator, and a 4500-gate 16*16 complex multiplier have been demonstrated using enhancement-mode n/sup +/-(Al,Ga)As/MODFETs, superlattice MODFETs, and doped channel heterostructure field-effect transistors (FETs) whose epitaxial layers were grown by molecular-beam epitaxy. With nominal 1- mu m gate-length devices, direct-coupled FET logic ring oscillators with realistic circuit structures have propagation delays of 30 ps/stage at a power dissipation of 1.2 mW/stage. In LSI circuit operation, these gates have delays of 89 ps/gate at a power dissipation of 1.38 mW/gate when loaded with an average fan-out of 2.5 gates and about 1000 mu m of high-density interconnects. High-performance voltage comparator circuits operated at sampling rates greater than 2.5 GHz at Nyquist analog input rates and with static hysteresis of less than 1 mV at room temperature. Fully functional 4-b analog-to-digital circuits operating at frequencies up to 2 GHz were obtained. >

Applications of superconducting interconnection in LSIs.

Advantages of superconducting interconnection in LSI circuit performance are discussed. Effective application areas of superconducting lines are signal lines for high drivability devices, power lines and chip to chip interconnection. Factors limiting the application such as cooling capacity and signal distortion due to multiple reflection are discussed. High frepuency characteristics of oxide superconductors and basic problems which should be overcome are also described.

Digital signal processing for improved NTSC television receiver

The authors have developed a digital signal processing approach for an improved NTSC (National Television System Committee) television (IDTV) system, utilizing three-dimensional motion adaptive processing techniques with frame memories. They made an effort to improve the precision of motion detection and introduced a stable system clock reproduction method and appropriate signal processing for nonstandard signals. The system has been implemented as digital LSI circuits, and an IDTV was made for home use. These digital signal processing techniques can help to improve the picture quality not only on large, direct viewing screens but also on projectors of more than 40 in.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A microprogrammable real-time video signal processor (VSP) for motion compensation

A video signal processor (VSP) LSI circuit with a three pipelined architecture has been developed for pattern matching, which is fundamental for the motion compensation necessary for teleconferencing systems. A high-speed arithmetic logic unit with absolute-value calculation capability and a minimum/maximum value detector, which are essential to pattern matching, have been integrated on the VSP LSI. The chip was fabricated with a 2.5- mu m CMOS and double-layer metallization technology. The number of MOSFETs integrated on the 9.91*9.50-mm/sup 2/ chip is about 48000. It operates at a 14.3-MHz clock frequency with a single 5-V power supply and typically consumes 240 mW. An experimental video signal processing system, using a single VSP LSI chip, is discussed. >

Full functionality of LSI gate arrays fabricated on 3-in-diameter, MOCVD-grown GaAs-on-silicon substrates

Fully functional, 504-gate arrays have been fabricated on an MOCVD (metalorganic chemical-vapor deposition)-grown, 3-in-diameter, GaAs-on-silicon substrate. Each ECL (emitter-coupled-logic)-compatible gate array consists of an eight-bit adder, a D flip-flop, a 214 divider (with a divide-by-four tap), and a 263-stage inverter string. These circuits represent 90% gate utilization, or approximately 6600 transistors. The wafer-level yield of fully functional gate arrays is 10.7%. This demonstrates total functionality and yield for a digital circuit with LSI-level complexity using MOCVD-grown GaAs-on-silicon material and shows that this material, even with defect densities greater than 108 cm/sup -2/, is viable for high-density LSI circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Waveform measurements in high-speed silicon bipolar circuits using a picosecond photoelectron scanning electron microscope

A description is given of a noncontact waveform measurement technique for the characterization of high-speed LSI and VLSI circuits using a picosecond photoelectron scanning electron microscope with 5-ps temporal resolution, 0.1- mu m spatial resolution, and a voltage resolution of 3 mV/ square root Hz. The ability of the technique to measure and monitor the internal waveforms and to resolve the different contributions of the delay in the circuit without any loading effect is demonstrated by its application to the full characterization of sub-100-ps silicon bipolar ECL (emitter-coupled logic) circuits. >

Fabrication and characteristics of NbN-based Josephson junctions for logic LSI circuits: S Yano, Y Tarutani, H Mori, H Yamada, M Hirano, U Kawabe (Hitachi Ltd., Tokyo, Japan) IEEE Trans. Magn. (USA), vol. MAG-23, no. 2, pp. 1472–1475 (March 1987). [received: 08 Sep. 1987] (1986 Applied Superconductivity Conference, Baltimore, MD, USA, 28 Sept.-3 Oct. 1986)

Fabrication and characteristics of NbN-based Josephson junctions for logic LSI circuits: S Yano, Y Tarutani, H Mori, H Yamada, M Hirano, U Kawabe (Hitachi Ltd., Tokyo, Japan) IEEE Trans. Magn. (USA), vol. MAG-23, no. 2, pp. 1472–1475 (March 1987). [received: 08 Sep. 1987] (1986 Applied Superconductivity Conference, Baltimore, MD, USA, 28 Sept.-3 Oct. 1986)

Growth and Characterization of Multilayered Structure of GaAs/Epi-Si/SiO2 /Si Composite

The monolithic integration of GaAs and Si devices is highly attractive for very high speed LSI and optoelectronic integrated circuits. To accomplish this, the epitaxial growth of GaAs films on Si substrates has been successfully realized. However, in the GaAs/Si structure, the conductive nature of the silicon substrate results in a severe transmission line loss [1,2]. To help solve this problem, we suggest to grow GaAs film on SOI (silicon on insulator) substrate for microwave device application. This GaAs/SOI structure will have low transmission line loss and excellent radiation hardness. In this paper, we present some cross-section SEM and TEM data and discuss the transmission line loss and radiation hardness of this multilayered structure.

APC-AB codec modules operating at 16 and 8 kbit/s

High-quality speech codec modules operating at 16 and 8 kb/s have been developed using an adaptive predictive coding with adaptive bit allocation (APC-AB) scheme. An optimized APC-AB algorithm is studied that reduces processing complexity while maintaining speech quality. The coding algorithm is implemented in two digital signal processors (DSPs). The DSP chips, a framing LSI circuit, a PCM codec, and some peripheral ICs are integrated in each of two compact packages, i.e. codec modules, operating at 16 or 8 kb/s. The codec module size is as small as 80 mm*50 mm*12 mm, and its typical power consumption is 500 mW using 2- mu m CMOS LSI technology. At 16 kb/s this APC-AB codec achieves high speech quality, close to that of a 7-bit mu -law PCM. The codec modules are expected to be used for various applications such as customer premises multiplexers for digital leased lines, digital mobile radio, and stored-and-forward-message systems (voice-mail systems). >