LSI Circuits Research Articles

A highly sensitive thermosensing CMOS Circuit Based on self‐biasing circuit technique

AbstractA thermosensing CMOS circuit that changes its internal voltage steeply at a critical temperature was developed. The circuit is based on a self‐biasing circuit technique and uses the temperature‐sensitive characteristics of MOSFETs operating in the subthreshold region. To develop this sensor device, a method to analyze self‐biasing circuits, which is different from a conventional one, was employed. This method is useful for understanding the self‐biasing circuit operation. A temperature sensor device makes use of a MOSFET resistor's transition from a strong inversion to a weak‐inversion or subthreshold operation. The temperature at which the transition occurs can be set to a desired value by adjusting the parameters of MOSFETs in the circuit. The sensor LSI can be made using a standard CMOS process and can be used as over‐temperature and over‐current protectors for LSI circuits. Copyright © 2009 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

Damage-Free Post-CMP Cleaning Solution for Low-<i>k</i> Fluorocarbon on Advanced Interconnects

As technology node progressing, ultra low-k film has been implemented to reduce RC delay in LSI circuit. A fluorocarbon (CFx) film is proposed as foreground ultra low-k film because of non-porous structure [1]. Although CFx film is expected to be stable for its structure advantage, damage-less process is anticipated to avoid dielectric constants change in subsequence process steps [2]. CMP and post CMP process are concerned to bring damage on devices, so the effect of post CMP cleaning solutions on CFx structure and electric property is evaluated.

Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors

Physical defects that are not covered by stuck-at fault or bridging fault model are increasing in LSI circuits designed and manufactured in modern Deep Sub-Micron (DSM) technologies. Therefore, it is necessary to target non-stuck-at and non-bridging faults. A stuck-open is one such fault model that captures transistor level defects. This paper presents two methods for maximizing stuck-open fault coverage using stuck-at test vectors. In this paper we assume that a test set to detect stuck-at faults is given and we consider two formulations for maximizing stuck-open coverage using the given test set as follows. The first problem is to form a test sequence by using each test vector multiple times, if needed, as long as the stuck-open coverage is increased. In this case the target is to make the resultant test sequence as short as possible under the constraint that the maximum stuck-open coverage is achieved using the given test set. The second problem is to form a test sequence by using each test vector exactly once only. Thus in this case the length of the test sequence is maintained as the number of given test vectors. In both formulations the stuck-at fault coverage does not change. The effectiveness of the proposed methods is established by experimental results for benchmark circuits.

Measurement-Based Analysis of Electromagnetic Immunity in LSI Circuit Operation

Impacts of electromagnetic (EM) interference (immunity) on operation of LSI circuits in a QFP-packaged and PCB-mounted environment are studied. EM power injection to a power-supply system leads to malfunction, where the power is translated into voltage bounces through combined on- and off- chip impedances, affecting power supply and ground, as well as signal nodes in a die, seen from on-chip waveform measurements. A lumped power-supply impedance model and the minimum amplitude of voltage bounce induced by EM power for malfunction, both of which can be derived from external measurements to a given packaged LSI, formulate an EM interference model that is helpful in the PCB design toward high immunity. The technique can be generally applied to systems-on-chip applications.

A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations

We have developed a circuit for determining an optimal supply voltage, VOPT, for which energy consumption will be minimized in devices suffering from high-leakage. This VOPT is determined on the basis of a trade-off between power consumption and operation time. Experimental results with a 90-nm CMOS device indicate that the proposed circuit successfully determines VOPT with high accuracy. VOPT operations with power gating at 40 MHz, and where VDD = 0.67 V, results in an energy reduction of 52.8% over that achieved with DVFS alone at 5 MHz (1/20 of maximum operational frequency). Further, we propose a scheme for suppressing determination error, one that results in voltage error of less than 50 mV.

Method for online nondestructive hardness assurance for CMOS LSI circuits realized in SOS technology

The radiation performance of digital CMOS circuits realized in SOS technology is investigated in relation to the radiation-induced charge at the silicon-sapphire interface. A nondestructive hardness-assurance method based on radiation annealing is proposed, and reasons are given why this approach should be feasible. The limits of applicability of the method are assessed.

A long reach digital subscriber loop transceiver

An echo-cancelling duplex transmission system is described for the digital subscriber loop which uses a 4-level zero redundancy line code (2B1Q) to give very long reach in the presence of crosstalk. Novel digital signal processing algorithms are used to simplify the analogue line interface circuitry. All the digital signal processing, along with sophisticated maintenance and interfacing circuitry, can be contained on a single LSI circuit. Measured performance results are presented.

BAST: BIST‐aided scan test. A new method for test cost reduction

AbstractIt is common to use ATPG of scan‐based design for high fault coverage in LSI testing. However, significant increases in test cost arise with increasing design complexity. Recent strategies for test cost reduction combine ATPG and BIST techniques. Unfortunately, these strategies have serious constraints. We propose a new method that employs ATE and BIST structures to apply coded test patterns to LSI circuits. Results obtained using practical circuits show drastic test cost reduction capability of the proposed method. © 2007 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 90(5): 58– 65, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.20356

Layout-Independent Transistor with Stress-Controlled and Highly Manufacturable Shallow Trench Isolation Process

In this paper, in order to obtain layout-independent transistors in recent fine-pitched LSI circuits, a completely stress-controlled shallow trench isolation (STI) process is proposed. In this process, a single-layered spin-on dielectric (SOD) film is used for STI gap filling without employing a complex hybrid structure. With this technique, the mechanical stress caused by STI is markedly suppressed. Subsequently, drain current (Id) modulation due to the STI stress is inhibited successfully. Thus, this technique is a very promising 45 nm node STI scheme with a high performance and a high reliability.

Between‐core vector overlapping for efficient core testing of system‐on‐chip LSI circuits

AbstractIn this paper, the authors propose a method for efficient parallel core testing for manufacturing testing of system‐on‐chip LSIs that consist of multiple full‐scan cores; this method is called “between‐core vector overlapping.” To shorten the time needed to test the entire SoC LSI, this uses a single bit sequence for test data (overlapped vector) obtained by overlapping test vectors of multiple cores as much as possible; during testing, this is fed jointly to each core, so that multiple cores can be tested in parallel. A key benefit of this method is that it minimizes the number of external input pins needed for testing multiple cores in parallel. To further reduce test times, the authors also propose methods for shortening the overlapped vectors: invert overlapping and split overlapping. Tests show these methods to be effective. © 2006 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 89(12): 53–62, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.20322

Inclusion-exclusion principle in the design of a BIST unit for LSI and VLSI circuits

The basic inclusion-exclusion algorithm is considered in the context of binary vectors. A connection is revealed between the algorithm and the generation of convolution codes for BIST applications in LSI and VLSI circuits. A strategy for changing from combinatorial identities to theoretical probabilities (with infinitely many vectors) is used to extend some classical relations of discrete mathematics and to investigate the results from the viewpoint of signature synthesis. It is shown that the inclusion-exclusion approach is not an identification algorithm in its own right, as it essentially gives the sum of i empirical probabilities.

100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet

A high-speed physical-layer architecture for Ethernet is described that supports 100-Gb/s throughput and 40-km transmission, making it well suited for next-generation metro-area and intrabuilding networks. Its links comprise 12 x 10-Gb/s synchronized parallel optical lanes. Ethernet data frames are transmitted by coarse wavelength division multiplexing link and bundled optical fibers. Ten of the lanes convey 640-bit data synchronously (64 bits x 10 lanes). One conveys forward error correction code ((132b, 140b) Hamming code), providing highly reliable (BER < 10 -12 ) data transmission, and the other conveys parity data, enabling faultlane recovery. A newly developed 64B/66B code-sequence-based deskewing mechanism is used that provides low-latency compensation for the lane-to-lane skew, which is less than 88 ns. Testing of this physical-layer architecture in a field programmable gate array circuit demonstrated that it can provide 100-Gb/s data communication with a 590k gate circuit, which is small enough for implementation in a single LSI circuit.

Applications of Bonding SOI Technology to High Performance LSI Circuits

not Available.

A nanoindentation instrument for mechanical property measurement of 3D micro/nano-structured surfaces

This paper presents a nanoindentation instrument for 3D micro/nano-structured surfaces made of soft metals such as LSI circuit patterns. The instrument can carry out indentations with high resolution in both the vertical direction (Z) and lateral directions (XY). An electro-polished tungsten probe with a tip diameter of 100 nm is used as the indenter. The indentation motion along the Z-direction is generated by a PZT actuator. The sample is mounted on the free-end of a steel cantilever. The indentation depth and load can be accurately obtained from the PZT displacement, cantilever spring constant and the cantilever deflection measured by a capacitance-type displacement sensor. Nanoindentation experiments are carried out on an aluminium sample in the vacuum chamber of a scanning electronic microscope. Experimental results demonstrate that the instrument has the ability to perform nanoindentation.

Lifetime prediction for submicrometer LSI circuits and programmable logic: An overview

An overview is given of the experience gained in lifetime prediction for submicrometer LSI circuits and programmable logic, as reported by leading manufacturers including Siemens AG, Analog Devices, Atmel, Xilinx, Altera, QuickLogic, and Actel. The main conclusions are as follows: (i) The Arrhenius equation remains a major tool for describing the temperature dependence of circuit lifetime. (ii) The lifetime of LSI circuits continues to display a bimodal pattern. (iii) Bias-temperature stressing constitutes a generally useful technique for identifying failure mechanisms. (iv) The chi-squared distribution should be employed in predicting useful-life failure rate.

A-combined approach to high-level synthesis for dynamically reconfigurable systems

The increase in complexity of programmable hardware platforms results in the need to develop efficient high-level synthesis tools since that allows more efficient exploration of the design space while predicting the effects of technology specific tools on the design space. Much of the previous work, however, neglects the delay of interconnects (e.g. multiplexers) which can heavily influence the overall performance of the design. In addition, in the case of dynamic reconfigurable logic circuits, unless an appropriate design methodology is followed, an unnecessarily large number of configurable logic blocks may end up being used for communication between contexts, rather than for implementing function units. The aim of this paper is to present a new technique to perform interconnect-sensitive synthesis, targeting dynamic reconfigurable circuits. Further, the proposed technique exploits multiple hardware contexts to achieve efficient designs. Experimental results on several benchmarks, which have been done on our DRL LSI circuit [M. Meribout et al. [200]], [M. Meribout et al. (1997)], demonstrate that, by jointly optimizing the interconnect communication, and function unit cost, we can achieve higher quality designs than is possible with such previous techniques as Force-Directed-Scheduling.

Modeling of High-Dose-Rate Pulsed Radiation Effects in the Parasitic MOS Structures of CMOS LSI Circuits

A theoretical analysis and a numerical simulation are reported of physical processes in the field oxide of CMOS circuits exposed to an ionizing-radiation pulse of high dose rate. Account is taken of (i) the field of radiation-generated charge carriers, (ii) the random distribution of the local field due to randomly scattered charges in the oxide, and (iii) geminate and bimolecular recombination. For weak and medium static applied fields, the dispersive transport of free holes is analyzed by the fractional Fokker–Planck equation, and a Monte Carlo simulation is conducted with regard to the oxide-charge field and the field dependence of hop times. The response of SOI oxide containing electron traps is considered. A method is proposed for the physical simulation of field-oxide radiation response at high dose rates. It consists in replacing pulsed irradiation at room temperature with steady-state irradiation at a low temperature.

A Study of Bending Effect on Pulse-Frequency-Modulation-Based Photosensor for Retinal Prosthesis

In this work, we study the effect of bending on the pulse-frequency-modulation (PFM)-based photosensor. Based on the results of our study of strain on metal oxide semiconductor field-effect transistor (MOSFET) devices, we explain the behavior of the photosensor under compressive and tensile bending. We found that the maximum frequency variation to bending is about +4% when extrapolated to the curvature of the human eye. From this study we hope to minimize or eliminate the effect of bending on LSI circuits. Although this study specifically deals with the PFM photosensor circuit, any other LSI circuit subjected to strain can be treated similarly.

New fabrication process for josephson tunnel junctions using photosensitive polyimide insulation layer for superconducting integrated circuits

Photosensitive polyimide, synthesized by block copolymerization, is expected to be an excellent insulation layer in LSI circuits in the future. This polyimide has a higher thermal resistance than those of the other organic polymers. It also has good electric properties such as a high break down voltage and a low dielectric constant. We propose a new fabrication process for the Josephson tunnel junction using a photosensitive polyimide. It is possible to simplify the fabrication process of the Josephson tunnel junction, because the photosensitive polyimide is used as the insulation layer instead of conventional inorganic insulation films without an etching process. We fabricated Nb/Al-AlOx/Nb Josephson tunnel junctions using this new process. The junctions show excellent current-voltage (I-V) characteristics with V/sub m/ values more than 80 mV.

New design methodology with efficient prediction of quality metrics for logic level design towards dynamic reconfigurable logic

The importance of efficient area and timing estimation is well established in high level synthesis (HLS) since it allows more efficient exploration of the design space while providing HLS tools with the capability of predicting the effects of technology specific tools on the design space. Much of the previous work has focused on estimation techniques that use very simple cost models based solely on functional units (FUs). Those models are not accurate enough to allow effective design space exploration since the effects of interconnects can indeed dominate the final design cost. The situation becomes even worst when the design is targeted to dynamically reconfigurable logic (DRL) technologies since the multiplexer delay may contribute heavily on the overall delay. In addition, large number of configurable logic blocks could be used for communication rather than for implementing FUs. In this paper we Present a new HLS design flow, which performs an accurate estimation on area and timing for DRL circuits. It takes into account not only FUs area and delay, but also the interconnection and communication effects. We select our DRL LSI circuit [M. Meribout, M. Motomura, Method for compiling high level programs into hardware, Japanese Patent: JSP2000-313818, 2000; M. Motomura et al., An embedded DRAM-FPGA chip with instantaneous logic reconfiguration, in: Symposium on VLSI Circuits, July 1997, pp. 55-56] as our main concentration. We tested our method with several benchmarks and the results show that we receive good performance of the design, with area and timing estimated efficiently.