LSI Chip Research Articles

特集 ＭＣＭ／ＬＳＩ実装技術 ＭＣＭ／ＬＳＩの実装技術の内外での動向

特集 ＭＣＭ／ＬＳＩ実装技術 ＭＣＭ／ＬＳＩの実装技術の内外での動向

Effect of temperature on stress-induced open failure in aluminum interconnects of LSIs

The effect of temperature on stress-induced open failure in aluminum interconnects of LSIs is numerically analyzed. Calculation parameters are annealing and reliability test temperatures. Hexahedra meshes are used to calculate thermal stress, elastic strain, plastic strain and creep strain as a function of process temperature and time. Changes in the shape of the LSI chip during the process is taken into account. The three types of temperature dependence of the failure lifetime reported previously can be explained by using a kinetic model in which the change in stress with time due to the creep strain is considered. It is found that reducing annealing temperature increases the failure lifetime. However, the effect saturates below the aluminum film deposition temperature.

VLSI in picture coding

Recent LSI technology development for motion video coding is described briefly. The standard coding algorithms discussed recently are based on interframe coding with motion compensation and DCT (Discrete Cosine Transform). LSIs for realizing the signal processing functions are shown as functions of integration scale and chip area. Custom design LSI chips for the interframe encoder and decoder, meeting the H.261 and MPEG standards, are shown. Also, progress of programmable video signal processors (VSP) are overviewed.

Conversion of sinusoidal frequencies to gray code

AbstractA method of straightforward conversion of sinusoidal frequency to Gray code expression is described. The unknown frequency is estimated using only the sign of the inverse cosine function. The frequency conversion error is shown by computer experiment. For a more accurate result, the majority decision principle and threshold logic, that is, a maximum likelihood estimator, are applied. Hardware implementation is so easy that the whole system can be implemented on an LSI chip.

Hot carrier evaluation of MOSFETs in ULSI circuits using the photon emission method

Photon emission from MOSFETs by hot carrier effect under AC operation is studied. A method to estimate the lifetime of MOSFETs in LSI chips, which uses the photon emission, is proposed. This method is based on experimental data showing that the lifetime of hot-carrier degradation is described by a universal curve with respect to the photon count at a wavelength of 200 nm. Quantitative estimations of lifetimes of MOSFETs in a real LSI are reported. This method is applied to the lifetime estimation of a CMOS microprocessor. >

Reliability improvement of polyimide‐insulated al‐alloy interconnection against package resin shrinkage stress

AbstractNew methods to reduce the deformation failure of the polyimide‐insulated multilevel interconnection and nondestructive measuring method to estimate the failure are presented. Deformation failure of the interconnection was found to be detected more sensitively by electrically measuring yields of via‐chain patterns of the two‐level interconnection located around test chip corners than by observing the first‐level Al‐alloy line deformation directly. Reduction of the alloy line failure was examined by analyzing which part of the resin causes the shrinkage stress which in turn causes the alloy line failure. It is shown that both improving the package resin adhesion to the LSI chip and using a resin with a smaller thermal expansion coefficient were remarkably efficient in reducing the alloy line deformation failure.

Development of mustrip gas chambers with multi-chip technology

We have developed the mustrip gas chamber (MSGC) by using multi-chip technology which supports high-density assembly of bare LSI chips on a silicon wafer. Our MSGC was operated steadily with ∼ 103 gain more than one week. An energy resolution of 15% for 5.9 keV X-ray of a 55Fe source was obtained. With a very thin polyimide substrate of 16 μm thickness, two interesting phenomena were observed; one was a strong dependence of gains on backplane potential, and the other was little time variation of gains. We also found that a guard mask of a thin polyimide layer on the cathode edge reduced incidental electrical discharges between anode and cathode strips.

Highly reliable Au-Sn eutectic bonding with background GaAs LSI chips : Masanori Nishiguchi, Noboru Goto and Hideaki Nishizawa. IEEE Trans. Compon. Hybrids mfg Technol.14(3), 523 (1991)

Highly reliable Au-Sn eutectic bonding with background GaAs LSI chips : Masanori Nishiguchi, Noboru Goto and Hideaki Nishizawa. IEEE Trans. Compon. Hybrids mfg Technol.14(3), 523 (1991)

Cache memories for data flow machines

Cache memories for dataflow machines are presented, and, in particular, four design principles for reducing the working set size of dataflow caches are introduced. They are (1) controlling the number of active state processes, (2) optimizing instruction addresses, (3) using a block-structured operand matching/waiting memory, and (4) making deterministic replacements. Based on these principles, instruction and operand caches are organized. A bypass control is also devised that enables cache block replacement to overlap with normal cache access. Miss ratio and performance of the caches are evaluated on a register transfer level simulator of a dataflow machine. The results show that the instruction cache of 1 k words and the operand cache of 2 k words achieve sufficiently low miss ratios. The bypass control compensates for the bandwidth of a narrow swapping channel to the extent that about eight dataflow processors with the caches can be integrated in an LSI chip.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 250-Mb/s, 700-mW, 32-highway*8-b S/P converter LSI with cross-access memory

A multihighway serial/parallel (S/P) converted LSI chip suitable for the broadband Integrated Services Digital Network (B-ISDN) node interface is presented. The chip, fabricated with 0.8- mu m BiCMOS technology, handles 32-highway*8 b of S/P, P/S conversion at up to 250 Mb/s and has a power dissipation of 700 mW. The chip features cross-access memory and a current-cut-type CMOS/ECL interface circuit. Each of these features is described and evaluated. A newly developed BiNMOS-type D-flip-flop (D-FF) is used to speed up the cross-access memory and is compared to a CMOS D-FF. >

The X-ray diffraction station at the ADONE wiggler facility: preliminary results (including crystal perfection)

The single-crystal X-ray diffractometer installed at the PWA Laboratory in Frascati is described. The Huber four-circle goniometer is controlled by an IBM-compatible personal computer by means of a plug-in board interface based on the LSI chip Am9513. The program CS running under MS-DOS performs a wide variety of operations from random search to data collection. The angular resolution of the diffractometer is 0.0025°, while the instrumental resolution at 8 keV, with an Si(lll) monochromator, is 0.0026°. After preliminary tests, 2Zn insulin crystals were mounted on the diffractometer and reflections were measured using synchrotron radiation. The rocking curves show full widths at half-maxima (FWHM) in the range 0.013–0.031° mainly due to the mosaicity.

ＬＳＩのオンチップ配線修正システムにおける集束イオンビーム加工技術の開発

During debugging logic LSIs, a period to reproduce LSI in order to change the logic design is becoming longer. To reduce the period from several weeks down to one day, an on-chip direct wiring modification system, using the focused ion beam (FIB) milling and the laser CVD, has been developed.This paper describes a precise FIB milling technique for cutting the wirings and making the via holes to the wirings of the LSI. Milling depth control by monitoring the ion induced photo-emissions and the milling strategy to overcome the surface steps of the LSI resulted in the milling depth accuracy of ±0.25μm. The system, consist of the FIB milling described in this paper and the laser CVD, has been applied to the logic modification of the LSIs of Hitachi M880 mainframe computer. Several tens of cuts, vias on an LSI chip were made by FIB, and the several jumper wirings were made by laser CVD. The average yield of modified LSI chips of 91.8% was achieved.

レーザＣＶＤによる低抵抗配線の高速形成

Experimental investigations concerning formation of metal interconnects on LSI chips using laser-induced CVD are described. Molybdenum conductors were deposited by pyrolytic decomposition of molybdenum hexacarbonyl using argon ion-laser irradiation. Increasing molybdenum hexacarbonyl pressure, increasing laser power and decreasing writing speed were accompanied by increasing width and thickness of molybdenum conductors. Decomposition efficiency is 20 to 30% which is higher than conventional thermal CVD. Increased width and thickness diminished the resistance of the conductors, but the resistivity was almost independent of the forming conditions and higher than that of bulk molybdenum. Auger electron spectroscopy revealed that the high resistivity of the as-deposited films was due to the presence of carbon and oxygen as impurities. These impurities are removable by laser annealing in a vacuum, whereby the resistivity can be reduced to 10 μΩ·cm. These low-resistivity conductors can be applied to fault analysis or repair of not only MOS devices but also linear and bipolar devices.

An image tracing approach using CMOS variable threshold logic

An image tracing processor, operated in combination with Bitmap-IV CAD and an extended memory bank, has been developed for broad feature analysis of binarized images on a bitmap plane. Broad 7 × 7 windows on the bitmap and threshold maps are applied to CMOS variable threshold logic (VTL), in order to perform an adaptive algorithm for tracing lines of the binarized image on the bitmap. The hardware was implemented on a breadboard and a CMOS LSI chip was designed. The tracing processor was applied to logic diagram recognition and its concept and performance were confirmed.

A high-speed halftoning processor for raster scanned images

A high-speed bilevel reproduction algorithm, called modified error diffusion (MED) algorithm, has been developed to provide high-quality halftoning images for continuous tone images and has been implemented in a CMOS LSI chip. The chip has been designed with standard-cell 1.5- mu m CMOS technology using an optimum layout design. The chip has achieved a maximum processing speed of 60 ns/pixel.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A wafer-scale-level system integrated LSI containing eleven 4-Mb DRAMs, six 64-kb SRAMs, and an 18 K-gate array

A system integrated LSI chip (SLSI) that contains eleven 4-Mb DRAMs, six 64-kb SRAMs, and an 18 K-gate array, for a graphics application system is described. To implement the SLSI on a silicon chip, three key techniques have been developed: (1) system redundancy for defect relief; (2) chip configuration and fabrication with blade masking to achieve a hybrid 38.16*50.4-mm/sup 2/ chip; and (3) large-capability and high-reliability 324-pin 54*86-mm/sup 2/ plastic pin grid array package. Using a system redundancy technique, a 60% yield for the SLSI is achieved with a 40% yield for the DRAM itself. That is twice the 30% yield of the conventional repair scheme. Access times are 65 ns for the DRAM and 14 ns for the SRAM with a 3.9-W chip power dissipation. >

Packaging technology for the NEC SX-3 supercomputers

Since the performance of a computer system is mainly related to the machine cycle time, improvement of the logic circuit delay is the key for high-speed operations. In order to show how to reduce the logic circuit delay, the characteristics required for LSI chips and packaging technologies are discussed and the technological trends in packaging and their limitations are considered. As a typical application of high-performance packaging technology, the NEC SX-3 Supercomputer packaging is introduced, featuring 9 in/sup 2/ polyimide-ceramic substrates, a microchip carrier, flipped TAB carrier (FTC), high-density multichip packaging, high-speed coaxial cable interconnections, and a water cooling system.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A one-chip ADC/DAC LSI for TV sound applications

A new LSI chip for digital TV sound applications was developed. A two-channel analog-digital converter, a two-channel digital-analog converter, digital filters, and a clock generator were totally implemented in one CMOS chip by means of digital technology. Each element was simplified as much as possible to achieve minimum chip size and was designed so as not to complicate the peripheral circuits. As a result, a simple and compact sound processing system was developed. The target performance data and the chip specifications are included. >

Two-bit microcomputer for educational use

A two-bit microcomputer as the simplest von Neumann computer system was used to provide experience in system integration for undergraduate electrical engineering students. Three areas were covered: construction on a board with PLDs, designing a set of physical masks with a CMOS logic compiler and fabricating an actual CMOS chip by a simplified CMOS wafer process. They accomplished the whole procedure, from designing to testing the CMOS digital LSI chip.

The design of a DFSA based pattern matcher

Abstract In order to eliminate the irrelevant data being transferred from disks into memory, many database machines adopt a data filter to filter out the irrelevant data on‐the‐fly. This paper proposes a new DFSA (Deterministic Finite State Automata) based pattern matcher to be implemented as the data filter. It can perform various searching operations, including fixed and variable length don't care patterns. The architecture of this pattern matcher is relatively simple and can be easily implemented by off‐the‐shelf LSI chips. In our design, it only requires one 16K×8 SRAM and five LSI chips for a given state transition table of 128 states. A test has been conducted to compare the performance of dBASE III and our data filter. The result shows that the data filter is, on average, five times better than the performance of dBASE III.