LSI Chip Research Articles

A special purpose LSI processor using the DDA algorithm for image transformation

A new special purpose processor, named MN8614, has been developed for the high speed execution of binary image transformations. The processor carrys out the processing based on a new extension of the DDA algorithm to reduce the number of multiplications required for image processing. In addition, a machine instruction set has been developed which makes optimal use of the new method. The processor is fabricated on a single LSI chip with 16-bit data paths. Although the basic chip design is the same as that used in the construction of a general purpose microprocessor, the processing speed of MN8614 proves to be more than 30 times faster.

Implementation of a Microprocessor-Based Access Controllers for a Multi-Drop Multi-Access Network

This paper describes the development of a microprocessor-based intelligent interface for handling the data link layer protocol in a multi Access Multi Drop Network. The development effort has the objective of producing an inteface board which will have the data source/destination on one side and the data network on the other. Apart from specifying the data destination, the user of this interface board will not be required to handle any of the other operational aspects of the network itself.The system being currently implemented is a modified SDLC Loop network capable of supporting one primary station (also acting as a gate way to other loops) and upto 254 secondary stations. The Network allows data link connections between any two stations in the network. For testing purposes the data rate supported by the loop is presently fixed at only 9.6 Kbps. Very minimal changes in hardware will allow upgrading the loop speed to 64 Kbps. This interface is being implemented using-standard LSI chips and other off-the-shelf components. The next planned upgrade is to change some of the LSI chips (and some of the interfacing software) in order to handle speeds of up to 880 Kbps.We have also started styding the implementation of a network using an Ethernet protocol with the objective of developing an interface board for it. This design effort also aims at using standard LSI Chips but not the Ethernet Controller device newly announced from INTEL. This design is still in its infancy and is likely to change as and when the Ethernet Controller devices are available.

Percussion envelope generator

First Page

A single-chip ADM LSI CODEC

This paper describes the circuit design of an ADM (adaptive delta modulation) LSI CODEC with filters. The LSI chip is mounted in a 16-pin DIP and can operate with single low voltage supply. In order to realize a low power dissipation LSI IC, switched capacitor technology was used in the design of input/output filters and integrators, and C-array D/A converters and low voltage analog circuits were developed. An operational amplifier with a complementary differential input stage and a comparator with a capacitor-coupled input stage were employed to obtain a wide input voltage range with a low voltage supply. This CODEC achieves speech quality higher than that of 6-bit μ-law PCM CODEC at 32 kbits/s and power dissipation of below 30 mW.

A Single-Chip ADM LSI CODEC

This paper describes the circuit design of an ADM (adaptive delta modulation) LSI CODEC with filters. The LSI chip is mounted in a 16-pin DIP and can operate with single low voltage supply. In order to realize a low power dissipation LSI IC, switched capacitor technology was used in the design of input/output filters and integrators, and C-array D/A converters and low voltage analog circuits were developed. An operational amplifier with a complementary differential input stage and a comparator with a capacitor-coupled input stage were employed to obtain a wide input voltage range with a low voltage supply. This CODEC achieves speech quality higher than that of 6-bit µ-law PCM CODEC at 32 kbits/s and power dissipation of below 30 mW.

GaAs Analog to Digital Converter and Memory IC's for Ultra High Speed Transient Recording

The excellent electron dynamical properties of gallium arsenide enable GaAs devices to achieve high speed performance levels many times those of corresponding silicon devices. These device performance advantages carry over into integrated circuit technologies as well, aided significantly by the fact that GaAs substrate material is available in semi-insulating (>108?cm) form for very low parasitics in monolithic integrated circuits. This has led to the achievement of logic delays as low as 12.8ps at 77°K or 16.8ps at 300°K in the more exotic GaAs IC approaches. In the standard 1?m gate length, planar MESFET GaAs circuits, ring oscillator delays of ?d=52ps at PD=1mw/gate have been demonstrated, increasing to ?d=70ps at PD=2mw/gate in MSI flip flop circuits (standard ftoggle=1/5?d type-D flip flops toggle up to nearly 3 GHz). The planar ion implanted GaAs MESFET circuits have been fabricated in circuit complexities up to 1008 logic gates, with NOR gate delays as low as 150ps obtained in these LSI chips (e.g., a 35?d multiply time of 5.25ns in 8×8 bit latched parallel multiplier circuits). These 1?m gate length MESFET circuits have been fabricated on up to 3? diameter GaAs wafers using the same type of DSW optical lithography used for silicon VLSI, which is considered ample evidence that this GaAs IC technology can be cost-effective and is ready for commercialization. This paper focuses on the application of this MESFET GaAs IC technology for the types of digital memory and analog to digital converter circuits required to implement ultra high speed transient recorders.

A Large Scale Hybrid Thermal Print Head

A high speed direct drive thermal print head, which prints across a 216 mm wide paper using 1728 heating resistor dots (8 dots/mm) has been developed.It can print 30 cm long paper in only a few seconds. The head consists of heating dots, over three hundred LSI chips, a couple of dozen capacitors and multilayer thin and thick film circuit substrate.The substrate is 240 &#215; 70 mm by 1.0 mm thick conductor line width/space is 50 <em>&#956;</em>/50 <em>&#956;</em>. Hybridizing heating elements, drivers and shift registers on one substrate has made it possible to transmit signals serially into the head.Therefore, the I/O pin number has become far smaller than the number of dots, which has eliminated intermittent I/O pin disconnection.

Thermal-conduction module cradles and cools up to 133 LSI chips : D. R. Barbour, S. Oktay and R. A. Rinne. Electronics, 143 (16 June 1982)

Orthodontic treatment with clear aligners is a quickly growing sector of orthodontic treatment. Both the increase in awareness of esthetics and the increase in orthodontic treatment demand from adults has fueled the demand for a more esthetic orthodontic treatment technique. The public demand for fast and esthetic treatment has been addressed by other dental sectors with approaches such as “instant orthodontics” in which crowns or veneers are used to mask malalignment or with products that claim to use “new techniques” to simply align anterior teeth without addressing other aspects of the occlusion that may need treatment to maintain a healthy dentition. Obviously, these types of approaches raise ethical concerns and the need to educate the public as to the shortfalls of these types of approaches. Fixed appliances have become smaller and more esthetically acceptable with the development of ceramic brackets, but they are still more noticeable than clear aligners. Dozens of companies worldwide now offer some type of clear aligner orthodontic product. While research has been done in the area of clear aligners, much of the early research was focused on trying to discredit the use of aligners as an option for orthodontic treatment except for minor crowding or spacing cases. Even so, there was some research that was done to further improve and progress the clear aligner technique. This is still a rapidly developing area and as a result, much of the literature consists of case reports.

A Wide-Band Satellite Microwave Switch Matrix for SS/TDMA Communications

A lightweight, broad-band, 8 × 8 crossbar microwave switch matrix (MSM) has been developed for satellite-switched timedivision multiple-access (SS/TDMA) operation anywhere in the 6 GHz up-link and/or 4 GHz down-link bands. The nearly transparent performance characteristics in the 3.5-6.5 GHz band, for any of the highly flexible interconnect possibilities, have been facilitated by the design of a low-power-consuming resistively matched PIN diode switch. Broad-band push-pull connectors are used to simplify assembly and disassembly of this modular three-dimensional matrix. The switch control electronics (SCE) circuits have been implemented as custom-designed LSI chips for integration within the MSM input distribution networks. Design considerations and performance characteristics of the satellite switch matrix are presented.

LSI chip for monochrome TV steals the show from multiple ICs : Gerald K. Lunn. Electronics, 143 (10 March 1982)

LSI chip for monochrome TV steals the show from multiple ICs : Gerald K. Lunn. Electronics, 143 (10 March 1982)

A single-chip NMOS analog front-end LSI for modems

Presents a fully integrated analog front-end LSI chip which is an interface system between digital signal processors and existing analog telecommunication networks. The developed analog LSI chip includes many high level function blocks such as A/D and D/A converters with 11 bit resolution, various kinds of SCFs, an AGC circuit, an external control level adjuster, a carrier detector, and a zero crossing detector. Design techniques employed are mainly directed toward circuit size reductions. The LSI chip is fabricated in a 5 /spl mu/m line double polysilicon gate NMOS process. Chip size is 7.14/spl times/6.51 mm. The circuit operates on /spl plusmn/5 V power supplies. Typical power consumption is 270 mW. By using this analog front-end LSI chip and a digital signal processor, modern systems can be successfully constructed in a compact size.

On-chip capacitance measurement circuits in VSLI structures

A precise capacitance measurement technique is described. This technique is based on a principle of capacitively divided ac voltage measurement. Details of the measurement procedure and test pattern configuration is also discussed. Utilizing the technique, precise capacitance measurements were carried out, which were practically difficult with direct measurements, and size effects of the small geometry capacitances were measured and evaluated. The technique was found to be practical and accurate, and besides, the test device can be integrated on an LSI chip, thus it appears to be very effective in VLSI development.

A 2500 gate bipolar macrocell array with 250 ps gate delay

An oxide-isolated walled-emitter structure has been developed to obtain high performance and high packing density. Using this process, a macrocell array having 2500 equivalent gates has been fabricated. A gate delay of 250 ps with a 1 mA current switch has been achieved. Special circuitry and macros have been incorporated on the LSI to enhance diagnostic capability at both the chip and the system levels. A pin array package with /spl theta//SUB JA//spl les/4/spl deg/C/W has been developed for the LSI chip.

An 8-bit single-chip microcomputer for automotive engine control

An 8-bit single-chip microcomputer μPD7811 for automotive engine control has been developed. This microcomputer has been improved both in its peripheral functions and its instruction set over existing single-chip microcomputers. It allows the conversion of the engine control system, which is composed of a number of LSI chips, to a single-chip configuration. It is now therefore possible to develop a compact reliable low cost engine control system. In this paper, the design target, the reinforced peripheral functions and the instruction set of the microcomputer are presented.

GaAs LSI chips aim at supplanting fastest silicon ICs: J. G. Posa Electronics p.39 (1980)

GaAs LSI chips aim at supplanting fastest silicon ICs: J. G. Posa Electronics p.39 (1980)

24- and 120-Channel Transmultiplexers Built with New Digital Signal Processing LSI's

Two new digital transmultiplexers intended for commercial use have been developed. One transmultiplexer performs a bilateral conversion between two 12-channel FDM group signals and a 24-channel PCM carrier signal. The other mutually connects two 60Channel FDM supergroup signals and five 24-channel or four 30channel PCM signals. Both exploit a block processing digital SSBFDM multiplex/demultiplex scheme employing a cascade of an FFT processor and a set of complex coefficient digital filters. They have been built using newly developed high-level DSP LSI chips. Algorithmic considerations, developed LSI architecture, and equipment configuration are described as well as digital processor design details and measured performance.

Access Charges and Related Issues for Civil GPS Users

The Global Positioning System (GPS) will be a giant navigation utility paid for by the U.S. taxpayers. Access charges will permit the operational costs to be borne by those who actually use the system, both foreign and domestic, rather than by the taxpayers. Civil users who pay for a service will not be ignored, as they are now with the Transit system. User charges will permit operational continuity when the DoD no longer needs GPS. An implementation technique based on annual replacement of an LSI chip which decrypts the satellite message is described. A low annual charge is recommended to permit maximum system use and to optimize annual revenues. Counterfeiting is shown to be impractical, except by pirate radio transmissions. The design challenges related to interaction with military requirements, equitable costs for different classes of users, and the transition from one access chip to the next are described. Institutional issues are outlined, including who should develop the user charge technique. It is proposed that higher charges apply to those who purchase foreign-built equipment to promote U.S. employment, balance of payments, and to provide a return on the U.S. taxpayer investment in the system development. Those civil users who need maxium accuracy are frustrated with the Government policy of accuracy denial. This is described, and the probable development of differential GPS techniques to recover accuracy is evaluated. The creation of differential GPS standards is encouraged. Finally, another plea for greater civil user involvement in federal navigation planning is aired.

A microprocessor based protocol converter for the direct connection of a mainframe to a packet switched network

This short note describes how a specific problem of connecting a large mainframe to an X.25 network has been solved by means of a microprocessor based device. The problem arises at the link level, because the hardware interface available does not have the capability of handling bit-oriented protocols. After a general description, the short note first shows how the problem can be properly handled, from the architectural point of view, with a sublayering of the said level. Then a brief description of the functionalities inside the microprocessor device is given, followed by an overview of the implementation, based on Z80 processor and a SIO-2 LSI chip. Finally, the article reports som considerations on the modalities for the insertion of this device, in order to minimize the impact on the throughput of the mainframe. The conclusion underlines how microprocessor devices can help in solving, in a cheap and effective way, communication problems otherwise very difficult to be managed.

Hardware sorter and its application to data base machine

The main contribution of this paper is the design of a hardware sorter. This sorter is configured as a balanced, fixed binary tree of node units; the configuration of the sorter is independent of the length of data to be sorted. Each node unit can be realized on a single LSI chip. The logic of the hardware sorter design is heavily influenced by a specific, compressed, representation of sorted data. Using this hardware sorter and a few auxiliary functions based on the sorted property, we demonstrate the design of a relational data base machine.

A Conduction-Cooled Module for High-Performance LSI Devices

The advent of LSI chip technology makes possible significantly increased performance and circuit densities by means of large-scale packaging of multiple devices on a single multi-layer ceramic (MLC) substrate. Integration at the chip and module levels has resulted in circuit densities as high as 2.5×10 7 circuits per cubic meter, with the necessity of removing heat fluxes on the order of 100 kW/m 2 . This paper describes the development and implementation of a novel packaging concept which meets the stringent and highly interactive demands on cooling, reliability, and reworkability of LSI technology. These requirements resulted in an innovative packaging approach, referred to as the thermal conduction module (TCM). The TCM uses individually spring-loaded “pistons” that contact each chip with helium gas, the conducting medium for removing heat efficiently. A dismountable hermetic seal makes multiple access possible for device and substrate rework, while ensuring mechanical and environmental protection of critical components. A wide range of thermal, mechanical, and environmental experiments are described with analytical and computer models. The one-dimensional approach used in the previous paper by Chu et al. is extended to three-dimensional computer modeling. Simulations of expected chip temperature distributions in the IBM 3081 Processor Unit are discussed. Enhanced thermal performance of the advanced packaging concept for future applications is also indicated.