A wafer-scale-level system integrated LSI containing eleven 4-Mb DRAMs, six 64-kb SRAMs, and an 18 K-gate array

Abstract

A system integrated LSI chip (SLSI) that contains eleven 4-Mb DRAMs, six 64-kb SRAMs, and an 18 K-gate array, for a graphics application system is described. To implement the SLSI on a silicon chip, three key techniques have been developed: (1) system redundancy for defect relief; (2) chip configuration and fabrication with blade masking to achieve a hybrid 38.16*50.4-mm/sup 2/ chip; and (3) large-capability and high-reliability 324-pin 54*86-mm/sup 2/ plastic pin grid array package. Using a system redundancy technique, a 60% yield for the SLSI is achieved with a 40% yield for the DRAM itself. That is twice the 30% yield of the conventional repair scheme. Access times are 65 ns for the DRAM and 14 ns for the SRAM with a 3.9-W chip power dissipation. >