Low Noise Amplifier Research Articles

RF-SOI Low-Noise Amplifier Using RC Feedback and Series Inductive-Peaking Techniques for 5G New Radio Application.

This paper presents a low-noise amplifier (LNA) with an integrated input and output matching network designed using RF-SOI technology. This LNA was designed with a resistive feedback topology and an inductive peaking technology to provide 600 MHz of bandwidth in the N79 band (4.4 GHz to 5.0 GHz). Generally, the resistive feedback structure used in broadband applications allows the input and output impedance to be made to satisfy the broadband conditions through low-impedance feedback. However, feedback impedance for excessive broadband characteristics can degrade the noise performance as a consequence. To achieve a better noise performance for a bandwidth of 600 MHz, the paper provided an optimized noise performance by selecting the feedback resistor value optimized for the N79 band. Additionally, an inductive peaking technique was applied to the designed low-noise amplifier to achieve a better optimized output matching network. The designed low-noise amplifier simulated a gain of 20.68 dB and 19.94 dB from 4.4 to 5.0 GHz, with noise figures of 1.57 dB and 1.73 dB, respectively. The input and output matching networks were also integrated, and the power consumption was designed to be 9.95 mA at a supply voltage of 1.2 V.

From Netlist to Manufacturable Layout: An Auto-Layout Algorithm Optimized for Radio Frequency Integrated Circuits

Layout stitching is a repetitive and tedious task of the radio frequency integrated circuit (RFIC) design process. While academic research on layout splicing algorithms mainly focuses on analog and digital circuits, there is still a lack of well-developed algorithms for RFICs. An RFIC system usually has a symmetrical layout, such as transmitter and receiver components, low-noise amplifier (LNA), an SPDT switch, etc. This paper aims to address this gap by proposing an automated procedure for the layout of RFICs by relying on the basic device/PCell structure based on the interconnection among circuit topologies. This approach makes the in-series generation of layouts and automatic splicing based on circuit logic possible, resulting in superior stitching performance compared with related modules in Advanced Design System. To demonstrate the physical application possibilities, we implemented our algorithm on an LNA and a switch circuit.

Author Correction: Multistep staircase avalanche photodiodes with extremely low noise and deterministic amplification

Author Correction: Multistep staircase avalanche photodiodes with extremely low noise and deterministic amplification

Ultra-Long-Span U-Band Transmission Enabled by Incoherently Pumped Raman Amplification

We demonstrate U-band Raman amplification in non-zero dispersion shifted fibre, exploiting the amplified spontaneous emission of an erbium-doped fibre amplifier as a broad-bandwidth, incoherent pump for low-noise amplification. By doing so, we achieve a high overall gain of ∼22 dB over a 3-dB bandwidth of ∼2.6 THz and obtain noise figures better than 4.3 dB and 5 dB in a 40km-long, discrete amplifier configuration, in forward pumped and backward pumped scenarios, respectively. The performance of the U-band Raman amplification is also studied through transmission of a coherent signal over a 285-km point-to-point link. This work represents, at the time of writing, the longest-reach single-span U-band transmission demonstrated.

A Tunable Gain and Bandwidth Low-Noise Amplifier with 1.44 NEF for EMG and EOG Biopotential Signal

This paper presents a low-noise inverter-based current-mode instrumentation amplifier with tunable gain and bandwidth for electromyogram (EMG) and electrooculogram (EOG) biopotential signals, targeting low input noise while maintaining low power consumption. The gain tuning method is based on pseudo-resistors, whereas the bandwidth is tunable due to a varactor system that is controlled by the same control voltage that tunes the gain. The circuit was designed and manufactured using the 110 nm UMC CMOS technology node, occupying an area of 0.624 mm2. The circuit presents a functioning mode for each biopotential signal with different characteristics, for the EMG a gain of 34.7 dB and a bandwidth of 1412 Hz was measured, with an input referred noise of 1.407 μV which matches a noise efficiency factor of 1.44. The EOG mode achieves a 39.5 dB gain and a 22.4 Hz bandwidth while presenting an input-referred noise of 0.829 μV corresponding to a noise efficiency factor of 6.37. For both modes, the supply voltage is 1.2 V and the circuit consumes 1 μA.

Quad path, CG-CS resistive feedback LNA architecture for 25–35 GHz band

In this paper, a Quad Path Noise Cancellation (QPNC) Low Noise Amplifier (LNA)presented for 5G sub-band 25-35GHz using GPDK 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology; which is composed of Common Source (CS) & Common Gate (CG) stages with resistive feedback and current reuse at the output. QPNC is used to cancel the noise of common gate transistors, which leads to reduce the noise fig. (NF). Resistive feedback is used to tradeoff between the input matching, gain, and NF i.e. overall refining the Figure of Merit (FoM) of the circuit. Mathematical analysis of impedance matching, gain, noise transfer function, and NF have been done using the small signal model of QPNC-LNA. Simulation has been done on Cadence Virtuoso software using GPDK 45 nm CMOS technology. Pre layout simulation result shows the minimum value of gain is 13.38 dB at 30.9GHz while the maximum value is 14.12 dB at 25.87GHz and flat over the entire frequency range. S11 i.e. input reflection coefficient is ranging from −16.16 dB at 25.21GHz to −11.52 dB at 35GHz for 50 Ω input impedance matching. NF value ranges from 2.69 dB at 25.69GHz to 3.77 dB at 35GHz. The IIP3 value for the proposed QPNC-LNA is 5.3 dB. For the four corners SS, SF, FS, and FF, process corner simulation has been performed. Post-layout simulation results depict the maximum value of gain is 12.71 dB at 25.75GHz. NF value is varying from 2.88 dB to 4.02 dB while the input reflection coefficient is ranging from −10.12 dB to −14.13 dB for 10GHz bandwidth. The circuit consumes 17.53 mW power at 1.2 V under a DC current of 14.61 mA, FoM1 is 8.36 dB and FoM2 of the proposed LNA is 49.35 dB. The layout of the proposed LNA is having an area of 0.03026mm2.

Low-Noise Amplifier for 5G Applications

Low-Noise Amplifier for 5G Applications

A compact 9–23 GHzlow noise amplifier with bandwidth extension techniques in 0.18‐μmSiGe BiCMOS

AbstractIn this paper, a novel wideband low noise amplifier (LNA) operating in the 9–23 GHz frequency range is presented. The proposed LNA design utilizes a combination technique consisting of pole‐tuning technique, shunt resistive‐capacitor negative feedback, and gate‐capacitive peaking technique to achieve significant bandwidth extension while maintaining acceptable overall performance. For verification, a one‐stage triple‐stacked LNA using the combination technique is designed and implemented in a 0.18‐μm SiGe BiCMOS heterojunction bipolar transistor (HBT) process. The fabricated prototype demonstrates a peak gain of 13.8 dB at 19.5 GHz, minimum noise figure of 3.1 dB at 14 GHz, 3‐dB bandwidth of 14 GHz, and a fractional bandwidth of 87.5%, while consuming a dc power of 39.6 mW. Moreover, the chip occupies a small silicon area of 0.39 mm2including all testing pads with a core size of only 0.192 mm2.

A SiGe HBT D-Band LNA Utilizing Asymmetric Broadside Coupled Lines

This letter presents a D-band low noise amplifier (LNA) implemented in 90 nm SiGe BiCMOS technology and is intended for next-generation communications systems. The LNA is a five-stage staggered common-emitter and cascode design used to simultaneously achieve wide bandwidth and high gain. The LNA utilizes asymmetric broadside coupled lines as interstage impedance transformers to achieve a wideband gain response while constraining power consumption. The presented LNA achieves an in-band gain of 26.5 dB and a bandwidth of 37.6 GHz. The minimum measured NF is 7.2 dB, and the dc power consumption is 20.6 mW. This D-band LNA achieves high gain, wide bandwidth, and low power consumption, resulting in a competitive performance with other D-band LNAs in the literature. The die area of the fabricated LNA is 0.8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 0.86 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> , including pads.

Design and Analysis of a 4.2 mW 4 K 6–8 GHz CMOS LNA for Superconducting Qubit Readout

This article proposes a cryogenic inverter-based low noise amplifier (LNA) for qubit readout. Its input impedance matching is realized by a high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> on-chip gate inductor and capacitive load through the gate-to-drain feedback capacitance of the input transistors. Cascode transistors are used to optimize the impedance matching, which results in a larger gate inductor and smaller load capacitor and hence a higher passive and inverter gain. Owing to the high passive gain and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> -factor of the gate inductor at 4 K, the noise of the active stages is substantially suppressed with a negligible noise contribution of the gate inductor. Moreover, with the current re-use in the inverter topology, less power consumption is achieved for the given transconductance of transistors. The input impedance, gain, and noise analyses of the proposed LNA are performed for room temperature (RT) operation, and its noise optimization is done by taking the cryogenic operation of the devices into account. We demonstrate with the circuit analysis and measurement results that the input impedance of the LNA has a low sensitivity to variations on device parameters at cryogenic temperatures. The LNA is implemented in a 28 nm CMOS technology. It achieves 0.4–0.7 dB noise figure (NF) with 4.2 mW power consumption at 4 K, and its operating frequency is between 6–8 GHz. The LNA consumes very low power compared to the state-of-the-art cryogenic CMOS LNAs while providing similar NF performance at 4 K, which makes it suitable for dilution refrigerators.

Bulk CMOS Low Noise Amplifier With Two Stage HPF Noise Matching Structure

In this study, a two-stage low-noise amplifier (LNA) was developed in which the noise-matching network of a high-pass filter (HPF) structure is applied to both stages. As the HPF noise matching network is used in both stages, the noise figure of the proposed LNA can be reduced compared to that of the conventional LNA. In particular, the noise figure is improved in the high-frequency region. To verify this development, a two-stage common-source LNA was implemented using 0.18-lm bulk complementary metal oxide semiconductor technology. The fabricated LNA achieved an average noise figure of 2.6 dB (minimum noise figure of 2.23 dB at 3.95 GHz) and a peak gain of 14.19 dB. In addition, the LNA has an input 1-dB compression point (IP1dB) of.12 dBm and a third-order input intercept point (IIP3) of +2.0 dBm at 3.5 GHz, consumes 16 mA with a 0.9 V supply, and has an area of 0.7 mm2.

Mutually coupled CG-CS current reuse low noise amplifier architecture for 4 – 14 GHz frequency

Abstract The current research paper presents a design of a mutually coupled cascode Common Gate Common Source (CG-CS) Low Noise Amplifier (LNA) using current reuse technique. The proposed design provides a significant improvement in the gain and noise performance of the LNA, while also reducing power consumption. Mutually coupled inductors help in reducing the size of the circuit while transformer connected at the output provide output impedance matching. Proposed LNA simulated for the 4–14 GHz RF frequency. Mathematical analysis of proposed LNA has been analyzed using the small signal model henceforth input impedance; gain and Noise Figure (NF) have been derived from it. The design and simulation results show that the proposed LNA design with current reuse technique achieved a maximum gain of 17.87 dB, minimum NF of 5.45 dB, and input reflection coefficient less than –10 dB for the 10 GHz bandwidth. These results indicate a significant improvement in the overall performance of the LNA compared to conventional designs as Figure of Merit (FoM) is 17.34.

Millimeter-Wave CMOS Low-Noise Amplifier With High Gain and Compact Footprint

For millimeter-Wave (mm-Wave) communications, this letter proposes a low-noise amplifier (LNA) topology by using gain-boosting and negative feedback techniques. In the proposed two-stage LNA, the first stage combines these two techniques to achieve a trade-off between gain and bandwidth. Following that, in the cascode structure, inductors are used to compensate for the parasitic capacitance of the transistors. To validate the proposed topology at a low cost, an mm-Wave LNA is designed and fabricated in a 180 nm CMOS process. Using two stages only, it achieves a maximum gain of 14.1 dB at 24.8 GHz, which is comparable to that of classical LNAs with three stages, and the chip footprint is reduced by 43%.

Design and Analysis of a Wideband K/Ka-Band CMOS LNA Using Coupled-TL Feedback

We demonstrate a low power (PD) 22-33 GHz CMOS low-noise amplifier (LNA) with low noise-figure (NF) and small group-delay (GD) variation for 28 GHz 5G system. Body-selfforward-bias (BSFB) technique, i.e., connection of transistor’s body to drain via body resistance, is used for threshold and supply voltage reduction, and substrate leakage suppression. Gain and NF enhancement at the same PD is achieved because lower VDD and higher transconductance (due to larger bias current) are used. Current-reused topology is used for low PD. Coupled transmission -line (TL) feedback neutralization technique is proposed for further gain and NF enhancement. The feedback from output (drain) to input (gate) via gate-drain capacitance (Cgd) can be cancelled by the feedback from drain (through source) to gate via the coupled TL and gate-source capacitance (Cgs). The LNA consumes 12.2 mW and achieves S21 of 16 dB, 3 dB bandwidth (f3dB) of 11 GHz (22-33 GHz), minimum NF (NFmin) of 2.5 dB, average NF (NFavg) of 3.1 dB, and GD variation of ±6 ps for 22-33 GHz, and figure-of-merit (FOM) of 91.7 GHz. Moreover, the LNA achieves input third-order intercept point (IIP3) of -3 dBm. The NF and FOM are one of the best results ever reported for LNAs with f3dB greater than 7 GHz and PD lower than 15 mW.

Low Power RF Low Noise Amplifier Design for 5G Wi-Fi Receiver

This paper presents the design of a differential Low Noise Amplifier (LNA) for a 5th generation Wi-Fi Receiver. The circuit is implemented with 90nm transistors using CMOS technology. The proposed differential LNA for 5G Wi-Fi (IEEE 802.11ac) is designed by combining two single-ended 5G Wi-Fi LNAs with optimized design values. The gate and source degenerated inductance values are optimized to achieve a 5GHz frequency of operation. Noise neutralization capacitors of 10pF are used to reduce the channel noise in the MOSFETs used in the circuit. The differential LNA achieves 93.6% input matching, an input impedance of 45.94Ω, a transducer gain of 25.76dB, a noise figure of 1.52dB, P1dB of -11.7dBm and IIP3 of 3.17dBm. Index Terms: CMOS, Noise Figure, 1dB compression point (P1dB), Third Order Input Intercept Point (II3), harmonic signal, ISM Band

A wideband CMOS LNA using noise‐canceling topology and gm‐boosting technique

AbstractIn this letter, a wideband low noise amplifier (LNA) using noise‐canceling topology and gm‐boosting technique is proposed. The noise‐canceling topology is used in the common gate (CG) amplifier to achieved better noise figure (NF) and wideband input matching. Meanwhile, the requirement of the input transconductance can be obviously decreased due to the application of gm‐boosting technique, which effectively alleviate the trade‐off between power consumption and voltage gain. The 3‐dB bandwidth of the LNA is from 2.1 to 4.1 GHz, covering widely used 5 G wireless communication frequency bands (n1, n7, n38, n41, n66, and n78 bands). The proposed LNA shows a flat and low measured NF of 3.3–3.6 dB within the operating bandwidth, while the peak power gain is 18.7 dB. The power consumption of this circuit is 16 mW with 1.2 V supply voltage, and the core area of the circuit is 0.066 mm2 with only one inductor for the whole chip.

28-GHz Bidirectional RF CMOS Amplifier Employing Body-Effect Control

This letter presents a 28-GHz bidirectional amplifier that operates as a low-noise amplifier (LNA) and a drive amplifier in the receiver (RX) (forward) and transmitter (TX) (backward) modes, respectively. In the proposed design, the bidirectional operation is realized through supply switching (SS) by utilizing the symmetric structure of a complementary metal–oxide–semiconductor (CMOS) device. Additionally, the body voltage control of an n-type MOS (nMOS) device is applied to attain symmetric and enhanced performance in both the forward and backward operations. The proposed design was fabricated using the 65-nm CMOS process and primarily characterized in the 28-GHz band. It achieves a nearly identical performance in both the forward and backward modes.

Dual-Photodiode Differential Receivers Achieving Double Photodetection Area for Gigabit-Per-Second Optical Wireless Communication

This article presents two dual-photodiode (PD) differential optical receivers that achieve double photodetection area to support gigabit-per-second optical wireless communication (OWC), while maintaining the receiver bandwidth. To enable differential light detection with a single incident light beam, a dual-PD OWC receiver architecture is proposed. In this architecture, two PDs are connected to the receiver complementarily without sacrificing the receiver bandwidth, and meanwhile, remain properly reversely biased. In addition, an adaptive dc photocurrent cancellation (ADPC) circuit is employed to prevent the saturation of the receivers under strong and imbalanced incident light. Based on the proposed architecture, two OWC receivers are implemented, including a proposed receiver and a reference one. In the proposed receiver, a low-noise shunt-feedback transimpedance amplifier (SF-TIA) with differential-pair-based current reuse and cross-coupled resistive feedback is proposed to enhance the sensitivity. In contrast, the reference receiver employs positive capacitive feedback to improve the transimpedance amplifier (TIA) performance. Both receivers have been fabricated with a standard 180 nm CMOS process and have been wire-bonded to two PDs. Experimental results indicate that both receivers can detect optical signals with data rates up to 2 Gb/s, and the proposed receiver architecture has significantly improved the bit error rate (BER) at 1.5 Gb/s from worse than 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-6}$</tex-math> </inline-formula> –10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-9}$</tex-math> </inline-formula> (error-free) with constrained optical power density. Moreover, the proposed receiver achieves an input sensitivity of 3.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> A <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{pp}}$</tex-math> </inline-formula> due to the superior performance of the proposed TIA, which outperforms the sensitivity of 10.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> A <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{pp}}$</tex-math> </inline-formula> from the reference receiver. Both sensitivities are measured at 1.5 Gb/s for a BER of 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-9}$</tex-math> </inline-formula> (error-free). The power consumption of the proposed and the reference receiver are 24.3 and 19.1 mW, respectively, excluding the output driver.

Quad-channel broadband compact multi-antenna GNSS down-converter for high-reliability navigation

Abstract A high-reliability broadband high-linearity down-converter for multi-antenna global navigation satellite system (GNSS) receiver is presented in this paper. Based on direction-of-arrival estimation, the multi-antenna GNSS receiver can separate the GNSS signals from the interfering signals and suppress harmful broadband radio frequency interferences. To drive the off-chip 50 Ω resistive load and meet the stringent requirements of linearity, a quad-channel down-converter with a broadband common-gate low-noise transconductance amplifier, current-driven passive mixer and novel bridge mode transimpedance driving amplifier have been proposed to contruct the multi-antenna receiver. The operating frequency of this down-converter is from 1.15 to 1.65 GHz, covering all bands for global positioning system (GPS), Beidou navigation satellite system (BDS), global navigation satellite system (GLONASS) and Galileo. The measured results show that the proposed quad-channel down-converter achieves +38 dBm output 3rd order intercept point (OIP3) and +17 dBm OP1dB (output-referred 1 dB compression point), 9.5 dB to 12.9 dB noise figure (NF) across the variable gain of 10 dB to 27 dB and approximately 47 dB channel isolation.

Harmonic analysis of CMOS low noise amplifier with employing PMOS IMD technique for biosensor applications

Harmonic analysis of CMOS low noise amplifier with employing PMOS IMD technique for biosensor applications