Quad path, CG-CS resistive feedback LNA architecture for 25–35 GHz band

Abstract

In this paper, a Quad Path Noise Cancellation (QPNC) Low Noise Amplifier (LNA)presented for 5G sub-band 25-35GHz using GPDK 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology; which is composed of Common Source (CS) & Common Gate (CG) stages with resistive feedback and current reuse at the output. QPNC is used to cancel the noise of common gate transistors, which leads to reduce the noise fig. (NF). Resistive feedback is used to tradeoff between the input matching, gain, and NF i.e. overall refining the Figure of Merit (FoM) of the circuit. Mathematical analysis of impedance matching, gain, noise transfer function, and NF have been done using the small signal model of QPNC-LNA. Simulation has been done on Cadence Virtuoso software using GPDK 45 nm CMOS technology. Pre layout simulation result shows the minimum value of gain is 13.38 dB at 30.9GHz while the maximum value is 14.12 dB at 25.87GHz and flat over the entire frequency range. S11 i.e. input reflection coefficient is ranging from −16.16 dB at 25.21GHz to −11.52 dB at 35GHz for 50 Ω input impedance matching. NF value ranges from 2.69 dB at 25.69GHz to 3.77 dB at 35GHz. The IIP3 value for the proposed QPNC-LNA is 5.3 dB. For the four corners SS, SF, FS, and FF, process corner simulation has been performed. Post-layout simulation results depict the maximum value of gain is 12.71 dB at 25.75GHz. NF value is varying from 2.88 dB to 4.02 dB while the input reflection coefficient is ranging from −10.12 dB to −14.13 dB for 10GHz bandwidth. The circuit consumes 17.53 mW power at 1.2 V under a DC current of 14.61 mA, FoM1 is 8.36 dB and FoM2 of the proposed LNA is 49.35 dB. The layout of the proposed LNA is having an area of 0.03026mm2.