Low Noise Amplifier Research Articles

Design of distributed impedance‐matching networks for ultra‐wideband low‐noise amplifiers

AbstractAn ultra‐wideband low‐noise amplifier (LNA) design was developed based on distributed network synthesis to achieve impedance matching of an active device by parasitic absorption. The equivalent device models of a low‐noise device were generated using negative‐image device modeling and traveling‐wave matching, and matching circuits were produced using the Chebyshev approximation. The minimum insertion loss and ripple of the matching networks were adjusted correctly to allow the parasitic absorption to match the device models. This paper describes the design methodology for distributed matching circuits and its application to the design of an ultra‐wideband LNA.

Co-Design of a Low-Noise Amplifier and SPDT SW for Band 42 T/R Modules with Low NF, High Gain, and 50-ohm Matching in Bulk CMOS Technology

Co-Design of a Low-Noise Amplifier and SPDT SW for Band 42 T/R Modules with Low NF, High Gain, and 50-ohm Matching in Bulk CMOS Technology

Two gm/ID design approaches for high-performance dual-resistive feedback noise-cancelling LNA

ABSTRACT In this article, a self-bias MOSFET-based dual-resistive feedback low-noise amplifier (LNA) is investigated. A detailed mathematical analysis of the addressed amplifier has been carried out using the return ratio-based feedback analysis technique. Furthermore, the LNAs have been simulated via Cadence using the TSMC 65 nm PDK. Two g m / I D strategies are described to handle the performance trade-offs for enhancing gain, noise figure (NF) and power consumption. The two strategies are conceptually similar to one another, with the selection of the transconductance efficiency being the only difference. While the first technique uses a transconductance efficiency to achieve the lowest power consumption while keeping an acceptable NF, the second strategy uses a particular transconductance efficiency for flawless noise cancelling without consideration for reduced power consumption. According to simulation results, the first recommended LNA has a voltage gain of 12 dB over a 3 dB bandwidth of 0.5–10 GHz, a minimal NF of 1.7 dB @ 7.014 GHz, a maximum NF of 1.932 dB @ 0.5 GHz, consumes 12.42 mW from a low supply voltage of 1.2 V and achieved a third-order intercept of −2.34 dBm @ 1 GHz. The simulation results of the second recommended LNA also show that it can operate with a low supply voltage of 1.2 V and still achieve a minimum NF of 0.978 dB @ 2.729 GHz, a maximum NF of 1.048 dB @ 6 GHz, II P 3 of 1.34 dBm and a voltage gain of 13 dB over a 3 dB bandwidth of 0.5–6 GHz with a consuming power of 25 mW.

Multi-head self-attention mechanism combined with feedforward network for time-varying nonlinear digital self-interference cancellation

In-band full duplex (IBFD) allows simultaneous communication in the same frequency band, thus significantly improving spectral efficiency. However, self-interference (SI) at the local transmitter affects decoding at the receiver, and SI intensity increases when the channel is time-varying. Existing techniques concentrate on dealing with digital self-interference (DSI) in static channels, which are difficult to adapt to time-varying environments. For this purpose, firstly, the recursive least squares (RLS) method is utilized to counteract linear DSI. Secondly, a new feedforward neural network based on the multi-head self-attention mechanism (MHSAM-FFNN) is designed to eliminate dynamically changing nonlinear DSI. RLS can track signals and update linear coefficients. The self-attention mechanism computes the attention between any two signals in a time-varying sequence and aggregates the temporal relations by the obtained attention weights. MHSAM-FFNN utilizes multiple self-attention modules in parallel, which enhances the acquisition of different effective information in the time-varying sequence to better learn the feature relationships between the current signal and other signals. It ultimately reconstructing the nonlinearity and memory effects of DSI. As tested in different time-varying environments, results show that this paper's scheme successfully reduces DSI to the noise floor. In addition, this paper considers two scenarios where both the power amplifier (PA) and the low noise amplifier (LNA) are nonlinear and where PA is nonlinear while LNA is linear. Results demonstrate that our scheme can achieve higher interference cancellation in different nonlinear scenarios.

The UmboMic: a PVDF cantilever microphone *

Objective. We present the ‘UmboMic,’ a prototype piezoelectric cantilever microphone designed for future use with totally-implantable cochlear implants. Methods. The UmboMic sensor is made from polyvinylidene difluoride (PVDF) because of its low Young’s modulus and biocompatibility. The sensor is designed to fit in the middle ear and measure the motion of the underside of the eardrum at the umbo. To maximize its performance, we developed a low noise charge amplifier in tandem with the UmboMic sensor. This paper presents the performance of the UmboMic sensor and amplifier in fresh cadaveric human temporal bones. Results. When tested in human temporal bones, the UmboMic apparatus achieves an equivalent input noise of 32.3 dB SPL over the frequency range 100 Hz–7 kHz, good linearity, and a flat frequency response to within 10 dB from about 100 Hz–6 kHz. Conclusion. These results demonstrate the feasibility of a PVDF-based microphone when paired with a low-noise amplifier. The reported UmboMic apparatus is comparable in performance to a conventional hearing aid microphone. Significance. The proof-of-concept UmboMic apparatus is a promising step towards creating a totally-implantable cochlear implant. A completely internal system would enhance the quality of life of cochlear implant users.

A Pseudo-Differential LNA with Noise Improvement Techniques for Concurrent Multi-Band GNSS Applications

A low-noise amplifier (LNA) design with the operation of concurrent dual-band for Global Navigation Satellite System (GNSS) receivers with single channel is presented in this work. This LNA structure has an inductively degenerated cascode architecture and is pseudo-differential, operating at two frequencies simultaneously (1.2 GHz and 1.57 GHz). Two noise reduction/cancellation techniques, using load capacitor and feedforward path, respectively, are proposed resulting in an excellent improvement in the noise figure (NF). The input matching circuit uses both series and parallel resonant components to enable concurrency. The adopted pseudo-differential structure results in input balun elimination. Inductively degenerated cascode topology provides both input impedance and optimum noise impedance matching. The soundness of the proposed approach has been demonstrated in a 0.18-µm CMOS technology by TSMC. Simulation results show that at 1.2 GHz and 1.57 GHz the LNA achieves −13 dB and −11 dB of input matching, 24.6 dB and 24.7 dB of gain, 1.47 dB and 1.43 dB of NF, respectively. The input-referred 1-dB compression point (IP1dB) is around −16 dBm, while the input-referred third-order intercept point (IIP3) achieves −2.2 dBm at 1.2 GHz and −0.6 dBm at 1.57 GHz. The LNA draws about 13 mA from a 1.8-V supply voltage.

A low-noise multipath operational amplifier with Gm-shared ping-pong and ripple averaging techniques

This paper presents a low-noise chopper-stabilized multipath operational amplifier with transconductance (Gm) sharing technique between ping-pong stages and ripple averaging technique. While the chopper stabilization is effective in reducing low-frequency noise and offset, output signals may yet contain ripples caused by the modulated amplifier offset. Several schemes can be implemented to suppress these output ripples; however, they require additional chip area and current consumption. The proposed ripple averaging technique effectively eliminates chopper ripples with very low additional power consumption of switched capacitors. To reduce the power consumption and circuit area, the Gm-shared ping-pong scheme is also proposed. The proposed circuit was implemented using a 0.18-μm CMOS process, with a total current consumption of 121.91 μA, and a supply voltage of 1.8 V. It occupies a chip area of 0.33 mm2 and exhibits an input-referred offset of 4.833 μV with a standard deviation 0.861 μV. The proposed amplifier has the input-referred noise level of 20.1 nV/√Hz.

Cryogenic bipolar low noise dc amplifier for low frequency applications

A low-noise bipolar differential dc amplifier was studied at temperatures of 300 and 77 K. It was shown that to ensure the best amplifier performance in terms of noise figure when the operating temperature decreases from 300 to 77 K, it is advisable to use the transistor in the mode of low currents not exceeding 2 mA. It has been established that lowering the operating temperature to 77 K leads to a decrease in the input resistance of the amplifier from a value of several kiloohms to 100 Ohms, the dynamic range increases from 80 to 85 dB, and the harmonic coefficient increases from 0.09% to 1%. In addition, lowering the operating temperature to 77 K has a significant effect on the noise properties of the amplifier: the spectral density of voltage noise decreases from 1 to 0.4 nV/Hz1/2, the spectral density of current noise increases from 2.5 to 9 pA/Hz1/2, while also The threshold frequencies of 1/f noise increase: for voltage from (0.1...10) to 20 Hz and for current from (10...100) to 1000 Hz. The possibility of using an amplifier for low-temperature measurements of samples with low input resistance is substantiated.

A 4-bit active-inductor-based digitally programmable low noise amplifier (AI-DPLNA) with a tunable and reconfigurable structure

In this paper, a band selective, active-inductor-based digitally programmable low noise amplifier (DPLNA) with a reconfigurable structure is presented. The reconfigurablility of the DPLNA is provided by a programmable current steering network, size-scalable cascode core, and input matching network, which are merged together, and along with a programmable active inductor (AI) as a replacement to huge passive inductors, a compact reconfigurable AI-DPLNA structure is achieved. The size-scalable source degenerated cascode structure is used as the core of the proposed DPLNA, and as a part of current steering network, its output current is reused for biasing the programmable active inductor (AI), which acts as the tank circuit for a narrow-band operation. The operation frequency of DPLNA is controlled by AI load and input matching circuit. A 2-bit programmable current steering network combined with the size-scalable cascode core set the operation frequency of the AI by adjusting its transconductance. Another 2-bits control the AI’s capacitance and also configure the input matching network. Using a TSMC 0.18μm CMOS technology, the simulated 4-bit AI-DPLNA gives a frequency band in the range from 1.816 GHz to 2.631 GHz, an input return loss (LRT) greater than 16.37 dB, a gain (S21) from 11 to 12.57 dB, and a minimum noise figure from 2.6 to 4.2 dB. It consumes a power of 11.4 mW to 12.3 mW from a 2 V supply, and occupies a silicon area of 0.0135 mm2. In addition to PVT and post layout simulations, a prototype of the DPLNA is implemented and tested using through-hole parts to verify the reconfigurability of the proposed structure.

A novel programmable gain control low noise amplifier (PGCLNA) design for automatic gain control loop in BLE applications

Bluetooth low energy (BLE) is a widely used short-range communication protocol and BLE receivers frequently encounter transient high-power RF (radio frequency) signals from antennas, leading to receiver saturation. To address this issue, this work proposes a 2.4 GHz programmable gain control low-noise amplifier (PGCLNA), which is a key element in an automatic gain control (AGC) system for BLE receiver applications. The proposed PGCLNA achieves discrete levels of gain using the g m -boosting technique by splitting the negative feedback. The proposed circuit is simulated in UMC 180 nm technology and the maximum gain achieved is 41.4 dB, with a step decrease of 15 dB in discrete levels. The gain variations do not degrade the performance of S11, which is always less than -16 dB. The noise figure (NF) is always minimum of 5.5 dB and in high gain mode, the minimum value of NF is 1.82 dB. The third-order intercept point (IIP3) is −7.621 dBm in the best circumstances and always remains above −10.69 dBm. These results are achieved by utilising 5.4 mW power at 1.8 V of supply voltage. The circuit occupies an area of 732 μm × 771 μm. The proposed PGCLNA design offers a solution to accommodate a wide range of input signals in BLE receivers, excellent gain control, low noise and robust performance characteristics, making it an essential component in an AGC system for BLE receiver applications.

Innovative techniques for achieving flat response in a dual-resonance ultra-wideband low-noise amplifier

This paper introduces a two-stage ultra-wideband low-noise amplifier (UWB-LNA) intended to be used in wireless communication systems. The architecture uses a novel double-resonance load network in the first stage and resistive shunt feedback in the second stage to achieve wide bandwidth with a flat response. A common gate stage at the input port seeks to present a high-impedance load to the single resonant network, while concurrently shunt negative feedback, source degeneration, and cascoded feedback schemes are used to improve performance. In this respect, the cascoded feedback provides flat gain across a wide bandwidth, while the source degeneration helps in impedance matching. Post-layout foot-print for the UWB-LNA designed and simulated using Cadence Virtuoso 180nm technology is 0.532 mm2 with an operating frequency 3.1–10.6 GHz incorporated. Operating on a 1.8 V supply voltage, it consumes 6 mW of power. The amplifier achieves a maximum gain of 18.75 dB, maintaining a flat low noise figure of 3.15 dB across frequencies ranging from 3.1 to 10.6 GHz. Stability analysis using the Roulettes test confirms the reliability of the proposed LNA, with Kf > 1 and Δ < 1.

Monolithic integrated circuit LNA 5–10 GHz

One of the features of the current stage of development of microwave electronics is the widespread use of monolithic integrated circuits. The interest of radio-electronic equipment developers in MIS is caused not only by better microwave characteristics compared to modules made using hybrid technology, but also by economic feasibility, ease of setup and reproducibility of parameters of finished products. An integral part of the transmitting and receiving paths of such systems are MMICs of low noise amplifiers. The goal of the work is to implement a matched MIC microwave low-noise amplifier with operating frequencies from 5 to 10 GHz with a noise figure of at least 1.2 dB and a gain of at least 20 dB. To develop an amplifier with operating frequencies up to 10 GHz, technology with a design standard of 0.25 microns was chosen. To meet the requirements, a two-stage circuit with automatic bias was selected. The widths of the transistors were selected taking into account the analysis of the minimum achievable noise figure and the balance between current consumption and output power. The autobias of the first stage is organized using an inductor. This solution allows not only to set the required DC mode, but also ensures input matching of the amplifier. The second stage is covered by negative feedback, which has a positive effect on the stability of the amplifier and its output matching. The amplifier supply voltage is 5 V, while resistors in the DC filter circuits set the required voltage value at the drain of each stage. Based on electrodynamic analysis, a topology was synthesized and an MIC was manufactured in the form of a gallium arsenide crystal 1.8 x 1.8 mm in size and 100 μm thick. An experimental study of manufactured LNA samples showed that in the frequency range from 5 GHz to 10 GHz the noise figure does not exceed 1.2 dB, while the minimum gain in the operating band is 21 dB. Characteristics of the amplifier has good temperature stability. The main parameters of the manufactured microcircuit are at the level of parameters of foreign analogues.

10 W-class, narrow-linewidth, linearly polarized, low-noise Holmium-doped Fiber Amplifier at 2095 nm

10 W-class, narrow-linewidth, linearly polarized, low-noise Holmium-doped Fiber Amplifier at 2095 nm

A low noise CLASS AB operational amplifier with high voltage output capability by 180 nm BCD process

Abstract In this work, a low noise CLASS AB operational amplifier, which can output high voltage, has been fabricated by a 180 nm BCD process. For the objective of achieving low noise, the bipolar junction transistor (BJT) input stage with the base current compensation structure is employed. Experimental results show that the low noise amplifier’s equivalent input current and voltage noise are 3.2 pA/sqrt (Hz) and 16.73 nV/sqrt (Hz) separately, and the rising and falling slew rates are 10.40 MV/s and 6.67 MV/s separately. With the die area of 0.629 mm2, the amplifier’s power consumption is 18.3 mW, which flows 60 μA on the 5 V low power supply and 600 μA on the 25 V high power supply.

Improving Amplification Bandwidth by Combining Josephson Parametric Amplifiers for Active Axion Search Experiments at IBS/CAPP

The Center for Axion and Precision Physics Research at the Institute for Basic Science in Republic of Korea is home to multiple active axion search experiments using cavity haloscopes that operate within the frequency range of 1–6 GHz. The haloscopes convert axions to photons, resulting in an output power of about 10-24\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$${^{-24}}$$\\end{document}–10-22\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$${^{-22}}$$\\end{document} W. To detect such a small signal amidst noise, quantum-limited noise amplifiers and ultra-low-temperature environment (a few tenths of mK) are required for all critical readout components to minimize noise from all active and passive lossy components. Our primary objective is to achieve the highest possible scanning-frequency speed, which includes the time for maintenance and system calibration. This paper presents the development and operation of low-noise amplifiers for haloscope experiments targeting different frequency ranges and provides design, operational, and performance details of the amplifiers.

A 16-channel Si probe monolithically integrated with CMOS chips for neural recording

Multi-channel neural electrodes as a crucial means are of great significance for information exchange between the brain and computers. Herein, we present a 16-channel Si-based active neural probe system that achieves a monolithic integration between the electrodes and circuits in a single probe, making it a standalone integrated electrophysiology recording system. The ASIC prepared on a base (2×2mm2) is a 16-channel analog frontend (AFE) for neural recording, and each channel has a low-noise amplifier (LNA), a bandpass filter (BPF), a buffer and a current bias circuit. The 258 neural signal recording electrodes (22×24μm2) are densely packed on a 50 μm thick, 100 μm wide, and 3 mm long shank. The ASIC of neural probe, internal interconnecting wires are all implemented in commercial SMIC 0.18 μm CMOS technology. The neural probe system achieves a 3.6 μVrms input-referred noise (IRN) in a bandwidth of 1.1Hz-10 kHz, 70.8 μW power consumption, 0.0785 mm2 area per channel, as well as an AFE gain of 58.1 dB Furthermore, the impedances of the Au electrodes can be obtained as 0.5–2.1 MΩ at a frequency of 1 kHz. The functionality of a 16-channel silicon-based neural probe is validated in an in-vivo experiment on lab rats.

An ultra‐low‐power low‐noise amplifier using a combination of current reuse and self‐forward body bias techniques for biomedical applications

SummaryLow‐power low noise amplifiers (LNAs) are critical block in the radio frequency (RF) front‐end of medical device radiocommunications service (MedRadio) receivers for amplifying weak received signals while introducing minimal noise. Despite the inherently low transconductance of MOS transistors, it is possible to achieve low noise, high gain, and good linearity in low power LNAs. This paper presents a combination of techniques to realize an ultra‐low‐power LNA with a compact size and high performance. The proposed LNA utilizes multiple gm‐boosting and self‐forward body bias techniques, with certain transistors operating in weak inversion. Additionally, the Multi‐Objective Inclined Planes System Optimization algorithm is employed to determine the optimal values of the circuit components, thereby achieving the best compromise among the various performance parameters. The proposed LNA with buffer is designed and simulated using an 180 nm CMOS process over the frequency band of 0.3–1 GHz. Simulated results show that the proposed LNA achieves a gain of 19.6 dB, a noise figure of 5.1 dB, good input matching (S11 &lt; −10 dB), and a third‐order intermodulation intercept point (IIP3) of 3.8 dBm. Additionally, it consumes 320 μW (without buffer) from a 1 V power supply, and the chip area is 235 μm × 372 μm. The simulated results demonstrate that the proposed ultra‐low power LNA is a promising candidate for biomedical applications.

Low-Profile Circularly Polarized HF Helical Phased Array: Design, Analysis, and Experimental Evaluation

This paper presents the design, development, and performance evaluation of a compact wideband phased array active helical antenna for monitoring HF interference. Traditional multi-element HF antenna designs are often subjected to size restrictions. The front-to-back ratio of the proposed circularly polarized phased array exceeds 20 dB across the operating range. This array enables the simultaneous monitoring of vertically and horizontally polarized signals, offering a practical alternative to larger antennas, particularly in space-constrained scenarios. Through advanced low-noise amplifier design, efficiency and bandwidth are optimized while mitigating mutual coupling effects. Optimal beamformer design enhances array performance with respect to more traditional array design approaches. The test results verify exceptional performance with an average axial ratio of 2 dB and a high front-to-back ratio beyond the desired frequency range. This study offers valuable insights into the design and deployment of compact wideband phased array antennas, providing an effective solution for monitoring HF interference.

The main directions of enhancement of digital antenna arrays

The development of modern radio electronic systems causes an increase in the requirements for the parameters of antenna devices (AU) and causes the transition from previously used mirror antennas and passive phased array antennas (FAA) to active FAA (AFAA), the considerable advantage of which is a significant reduction in energy losses of transmitted and received signals by reducing the distance of the low-noise amplifier input and output of power amplifier to the antenna element. Further development of the AU is the transition from AFAA with analog beamforming to digital antenna arrays (DAR) with digital beamforming, the advantages of which are due to the possibility of forming multibeam receiving and transmitting radiation patterns with independent control of the direction and shape of the beams, as well as the possibility of flexible change of operating modes. The use of a DAR with two-dimensional electronic scanning provides a significant increase in the efficiency of radio-electronic systems. Thus, their use in radar provides a gain in the efficiency of using the time, energy, frequency and spatial resources of radar with CAR up to 13 times compared with radar with passive FAA and AFAA with one-dimensional scanning. The disadvantages of the DAR are the high cost and increased energy consumption due to the installation of active elements in each transceiver channel, as well as the long time required to create new products, associated with a large amount of software and a complex structure for building a CAR. To overcome these disadvantages, manufacturers of antenna arrays and developers of the radio-electronic element base are creating new technical solutions. The main directions of development of technologies for the production of DAR functional devices that reduce the cost and reduce the time needed to create new products are shown: the development of common modules that allow you to create scalable DAR, increasing the integration of microwave monolithic integrated circuits with the placement of the maximum number of transceiver channels on one chip, increasing the integration of ASIC, including ADCs, DACs and digital signal processing devices, increasing the clock frequencies of digital functional nodes, as well as the development of circuit solutions for building nodes with low energy consumption.

A mm‐wave LNA employing current re‐use and non‐linearity cancellation in 28 nm CMOS for automotive RADAR and 6G receivers

AbstractThis letter reports an 85 GHz low noise amplifier (LNA) employing derivative superposition based non‐linearity cancellation and a current re‐use topology. The LNA employs a two‐stage stacked architecture, each featuring neutralized differential pairs utilizing the same DC current. In derivative superposition, an auxiliary branch consisting of neutralized differential pairs cells is added in the LNA in parallel to stage 1 to ensure non‐linearity cancellation. Layout‐based capacitive neutralization is implemented to improve GMAX, resulting in simplified routing, reduced parasitics, and a more compact layout. The proposed LNA is fabricated in TSMC 28 nm CMOS process and achieves a peak gain of 8.4 dB at 84.2 GHz with a measured 3 dB bandwidth () from 79.4 to 92 GHz. The minimum measured noise figure is 12.8 dB. The LNA draws 34 mA of DC current from a 1.2 V supply. The highly linear LNA with IIP3 +6.5 dBm is tailored for automotive RADAR and 6G receivers.